User contributions
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- 13:52, 25 June 2019 (diff | hist) . . (+306) . . L2 and Directory cache controller (→Message Generator)
- 13:47, 25 June 2019 (diff | hist) . . (+1) . . L2 and Directory cache controller (→Replacement Logic)
- 13:47, 25 June 2019 (diff | hist) . . (-141) . . L2 and Directory cache controller (→Replacement Logic)
- 13:13, 25 June 2019 (diff | hist) . . (-36) . . L2 and Directory cache controller (→Replacement Logic)
- 13:01, 25 June 2019 (diff | hist) . . (-254) . . L2 and Directory cache controller (→Cache Update Logic)
- 12:54, 25 June 2019 (diff | hist) . . (-236) . . L2 and Directory cache controller (→TSHR Update Logic)
- 12:49, 25 June 2019 (diff | hist) . . (+99) . . L2 and Directory cache controller (→Protocol ROM)
- 12:49, 25 June 2019 (diff | hist) . . (+10) . . L2 and Directory cache controller (→Protocol ROM)
- 12:47, 25 June 2019 (diff | hist) . . (+1,691) . . L2 and Directory cache controller (→Stage 3)
- 12:33, 25 June 2019 (diff | hist) . . (-4) . . L2 and Directory cache controller (→Stage 2)
- 12:28, 25 June 2019 (diff | hist) . . (+24) . . L2 and Directory cache controller (→Stage 1)
- 12:19, 25 June 2019 (diff | hist) . . (+2) . . L2 and Directory cache controller (→Stage 1)
- 12:04, 25 June 2019 (diff | hist) . . (+21) . . L2 and Directory cache controller
- 11:58, 25 June 2019 (diff | hist) . . (+13) . . L1 Cache Controller (→Cache Update Logic)
- 11:50, 25 June 2019 (diff | hist) . . (+36) . . L1 Cache Controller (→MSHR Update Logic)
- 11:43, 25 June 2019 (diff | hist) . . (+6) . . L1 Cache Controller (→Replacement Logic)
- 11:40, 25 June 2019 (diff | hist) . . (+3) . . L1 Cache Controller (→Issuing a Request)
- 11:39, 25 June 2019 (diff | hist) . . (-4) . . L1 Cache Controller (→Request Issue Signals)
- 11:39, 25 June 2019 (diff | hist) . . (+358) . . L1 Cache Controller (→Stage 1)
- 11:28, 25 June 2019 (diff | hist) . . (-4) . . L1 Cache Controller (→Assumptions)
- 18:32, 21 June 2019 (diff | hist) . . (-102) . . L1 Cache Controller (→MSHR Update Logic)
- 18:18, 21 June 2019 (diff | hist) . . (+174) . . L1 Cache Controller (→Replacement Logic)
- 18:06, 21 June 2019 (diff | hist) . . (-34) . . L1 Cache Controller (→Protocol ROM)
- 17:20, 21 June 2019 (diff | hist) . . (+83) . . L1 Cache Controller (→Protocol ROM)
- 17:17, 21 June 2019 (diff | hist) . . (+28) . . L1 Cache Controller (→MSHR)
- 17:14, 21 June 2019 (diff | hist) . . (-110) . . L1 Cache Controller (→Hit/miss logic)
- 17:07, 21 June 2019 (diff | hist) . . (+27) . . L1 Cache Controller (→Requests Scheduler)
- 17:05, 21 June 2019 (diff | hist) . . (+2) . . L1 Cache Controller (→Request Issue Signals)
- 17:05, 21 June 2019 (diff | hist) . . (+1) . . L1 Cache Controller (→Request Issue Signals)
- 16:54, 21 June 2019 (diff | hist) . . (+64) . . L1 Cache Controller (→Request Issue Signals)
- 16:48, 21 June 2019 (diff | hist) . . (+377) . . L1 Cache Controller (→Stall Protocol ROMs)
- 16:45, 21 June 2019 (diff | hist) . . (-25) . . L1 Cache Controller (→Stall Protocol ROMs)
- 16:38, 21 June 2019 (diff | hist) . . (+4) . . L1 Cache Controller (→MSHR Signals)
- 16:37, 21 June 2019 (diff | hist) . . (0) . . L1 Cache Controller (→Assumptions)
- 16:36, 21 June 2019 (diff | hist) . . (+3) . . L1 Cache Controller (→Assumptions)
- 16:36, 21 June 2019 (diff | hist) . . (+26) . . L1 Cache Controller
- 16:31, 21 June 2019 (diff | hist) . . (+15) . . MSI Protocol (→The key role of MC_Ack)
- 16:27, 21 June 2019 (diff | hist) . . (+80) . . MSI Protocol (→The key role of MC_Ack)
- 16:07, 21 June 2019 (diff | hist) . . (+24) . . MSI Protocol (→The key role of MC_Ack)
- 16:04, 21 June 2019 (diff | hist) . . (+344) . . MSI Protocol (→Transitions of state N)
- 15:55, 21 June 2019 (diff | hist) . . (-115) . . MSI Protocol (→Limited directory memory)
- 15:49, 21 June 2019 (diff | hist) . . (+27) . . Network interface (→General architecture)
- 15:47, 21 June 2019 (diff | hist) . . (+10) . . Network (→Data structures)
- 15:28, 21 June 2019 (diff | hist) . . (+34) . . MC Item (→Running threads) (current)
- 15:28, 21 June 2019 (diff | hist) . . (+9) . . MC Item (→Setting PCs)
- 15:27, 21 June 2019 (diff | hist) . . (+1) . . MC Item
- 15:25, 21 June 2019 (diff | hist) . . (+7) . . Heterogeneous Tile (→Adding custom logic)
- 15:24, 21 June 2019 (diff | hist) . . (+22) . . Heterogeneous Tile (→Synchronization Interface)
- 15:23, 21 June 2019 (diff | hist) . . (+11) . . Heterogeneous Tile
- 15:21, 21 June 2019 (diff | hist) . . (+18) . . MC System (→H2C tile)
- 15:21, 21 June 2019 (diff | hist) . . (+1) . . MC System (→MC tile)
- 15:21, 21 June 2019 (diff | hist) . . (+8) . . MC System (→MC tile)
- 15:20, 21 June 2019 (diff | hist) . . (+9) . . MC System (→NPU tile)
- 15:19, 21 June 2019 (diff | hist) . . (+41) . . MC System (→NPU tile)
- 15:18, 21 June 2019 (diff | hist) . . (+9) . . MC System (→NPU tile)
- 15:17, 21 June 2019 (diff | hist) . . (+7) . . MC System (→NPU tile)
- 15:15, 21 June 2019 (diff | hist) . . (-1) . . Core (→Result Composer)
- 15:14, 21 June 2019 (diff | hist) . . (+535) . . Core (→Result Composer)
- 15:13, 21 June 2019 (diff | hist) . . (+647) . . Core (→Result Composer)
- 15:10, 21 June 2019 (diff | hist) . . (+1,512) . . Core (→Writeback stage)
- 15:07, 21 June 2019 (diff | hist) . . (+69) . . Core (→Result Composer)
- 14:56, 21 June 2019 (diff | hist) . . (-1) . . Synchronization (→Barrier Synchronization Protocol) (current)
- 14:48, 21 June 2019 (diff | hist) . . (-111) . . Scratchpad unit
- 14:47, 21 June 2019 (diff | hist) . . (+1,821) . . Core (→Control registers)
- 14:27, 21 June 2019 (diff | hist) . . (-15) . . Core (→Cache Pseudo-LRU)
- 14:27, 21 June 2019 (diff | hist) . . (+70) . . Core (→Cache Pseudo-LRU)
- 14:26, 21 June 2019 (diff | hist) . . (+647) . . Core (→Cache Pseudo-LRU)
- 14:21, 21 June 2019 (diff | hist) . . (+26) . . Basic comps (→Memory Banks)
- 14:20, 21 June 2019 (diff | hist) . . (+182) . . Basic comps
- 14:15, 21 June 2019 (diff | hist) . . (0) . . Include (→Synchronization Defines)
- 14:15, 21 June 2019 (diff | hist) . . (+36) . . Include (→Synchronization Defines)
- 14:14, 21 June 2019 (diff | hist) . . (+50) . . Include (→Scratchpad Memory Defines)
- 14:13, 21 June 2019 (diff | hist) . . (+16) . . Include (→User Defines)
- 14:13, 21 June 2019 (diff | hist) . . (+27) . . Include (→NPU Defines)
- 14:12, 21 June 2019 (diff | hist) . . (+12) . . Include (→Coherence Defines)
- 14:11, 21 June 2019 (diff | hist) . . (+5) . . Include (→Synchronization Defines)
- 14:10, 21 June 2019 (diff | hist) . . (+24) . . Include (→Network Defines)
- 14:09, 21 June 2019 (diff | hist) . . (+5) . . Include (→Scratchpad Memory Defines)
- 14:08, 21 June 2019 (diff | hist) . . (-20) . . Include (→NPU Defines)
- 14:07, 21 June 2019 (diff | hist) . . (+38) . . Include (→User Defines)
- 14:06, 21 June 2019 (diff | hist) . . (+11) . . Include
- 14:04, 21 June 2019 (diff | hist) . . (0) . . The NaplesPU Hardware architecture (→Tile Overview)
- 14:01, 21 June 2019 (diff | hist) . . (-1) . . Main Page (→simulate.sh script)
- 14:00, 21 June 2019 (diff | hist) . . (-1) . . Main Page (→setup_project.sh script)
- 13:57, 21 June 2019 (diff | hist) . . (-6) . . Main Page (→Getting started)
- 17:04, 20 June 2019 (diff | hist) . . (-44) . . MSI Protocol
- 16:58, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . N File:MSI Protocol dc-rom new.png (current)
- 16:57, 20 June 2019 (diff | hist) . . (-3) . . MSI Protocol (→Directory Controller)
- 15:38, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:38, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:37, 20 June 2019 (diff | hist) . . (0) . . File:MSI Protocol cc-rom p2 new.png (Mirko uploaded a new version of File:MSI Protocol cc-rom p2 new.png) (current)
- 15:37, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Cache Controller)
- 15:36, 20 June 2019 (diff | hist) . . (0) . . N File:MSI Protocol cc-rom p2 new.png
- 15:36, 20 June 2019 (diff | hist) . . (-3) . . MSI Protocol (→Cache Controller)
- 15:32, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:32, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Cache Controller)
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