User contributions
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- 17:23, 25 July 2019 (diff | hist) . . (-3) . . Programming Model (→NaplesPU Vector intrinsics) (current)
- 17:02, 25 July 2019 (diff | hist) . . (+1,524) . . Programming Model (→NaplesPU Intrinsics)
- 16:57, 25 July 2019 (diff | hist) . . (+27) . . Programming Model
- 16:46, 25 July 2019 (diff | hist) . . (+44) . . Programming Model (→Barrier Instruction)
- 16:46, 25 July 2019 (diff | hist) . . (+1,637) . . Programming Model (→NaplesPU Other Aspects)
- 16:42, 25 July 2019 (diff | hist) . . (+10) . . Programming Model (→NaplesPU Vector intrinsics)
- 16:41, 25 July 2019 (diff | hist) . . (+1,268) . . Programming Model (→NaplesPU Vector intrinsics)
- 16:36, 25 July 2019 (diff | hist) . . (+860) . . Programming Model (→NaplesPU Vector intrinsics)
- 16:34, 25 July 2019 (diff | hist) . . (+329) . . Programming Model (→Standard LLVM intrinsics)
- 16:33, 25 July 2019 (diff | hist) . . (+199) . . Programming Model (→NaplesPU Other Aspects)
- 16:03, 25 July 2019 (diff | hist) . . (-1) . . Programming Model (→NaplesPU Vector intrinsics)
- 15:57, 25 July 2019 (diff | hist) . . (+291) . . Programming Model (→NaplesPU Vector intrinsics)
- 15:50, 25 July 2019 (diff | hist) . . (+6) . . Programming Model (→NaplesPU Vector intrinsics)
- 15:49, 25 July 2019 (diff | hist) . . (+403) . . Programming Model (→NaplesPU Vector intrinsics)
- 15:27, 25 July 2019 (diff | hist) . . (+1,417) . . Programming Model (→NaplesPU Other Aspects)
- 11:12, 12 July 2019 (diff | hist) . . (+347) . . L2 and Directory cache controller (→Replacement Logic) (current)
- 11:19, 8 July 2019 (diff | hist) . . (-57) . . Scratchpad unit (→Kernel example: matrix multiplication)
- 14:55, 2 July 2019 (diff | hist) . . (+12) . . MC System (→MC tile) (current)
- 14:12, 2 July 2019 (diff | hist) . . (-3) . . MC System (→NPU tile)
- 12:34, 2 July 2019 (diff | hist) . . (-2) . . Network router (→First stage) (current)
- 12:05, 2 July 2019 (diff | hist) . . (-9) . . Network interface (→Rebuilt packets queue) (current)
- 15:21, 1 July 2019 (diff | hist) . . (-12) . . L1 Cache Controller (→Stall Protocol ROMs) (current)
- 15:16, 1 July 2019 (diff | hist) . . (-2) . . L1 Cache Controller
- 13:20, 1 July 2019 (diff | hist) . . (-1) . . Include (→Network Defines) (current)
- 13:15, 1 July 2019 (diff | hist) . . (+95) . . Include (→User Defines)
- 13:13, 1 July 2019 (diff | hist) . . (+5) . . SC Logger (current)
- 13:11, 1 July 2019 (diff | hist) . . (0) . . The NaplesPU Hardware architecture (→Configuring NaplesPU) (current)
- 13:10, 1 July 2019 (diff | hist) . . (+126) . . Heterogeneous Tile (→Service Message Interface) (current)
- 13:06, 1 July 2019 (diff | hist) . . (-2) . . Heterogeneous Tile (→Service Message Interface)
- 13:06, 1 July 2019 (diff | hist) . . (+96) . . Heterogeneous Tile (→Service Message Interface)
- 13:04, 1 July 2019 (diff | hist) . . (-4) . . Heterogeneous Tile (→Service Message Interface)
- 13:04, 1 July 2019 (diff | hist) . . (+4) . . Heterogeneous Tile (→Service Message Interface)
- 13:03, 1 July 2019 (diff | hist) . . (+2,945) . . Heterogeneous Tile
- 12:36, 1 July 2019 (diff | hist) . . (-82) . . Extending NaplesPU (→SystemVerilog coding NaplesPU guidelines) (current)
- 15:38, 28 June 2019 (diff | hist) . . (-1) . . ISA (→M type instructions) (current)
- 15:38, 28 June 2019 (diff | hist) . . (+149) . . ISA (→M type instructions)
- 15:35, 28 June 2019 (diff | hist) . . (-348) . . ISA (→M type instructions)
- 15:34, 28 June 2019 (diff | hist) . . (+331) . . ISA (→M type instructions)
- 15:21, 28 June 2019 (diff | hist) . . (+6) . . ISA (→M type instructions)
- 15:21, 28 June 2019 (diff | hist) . . (0) . . N File:M format new.png (current)
- 15:21, 28 June 2019 (diff | hist) . . (-6) . . ISA (→M type instructions)
- 15:20, 28 June 2019 (diff | hist) . . (+4) . . ISA (→M type instructions)
- 15:19, 28 June 2019 (diff | hist) . . (+6) . . ISA (→M type instructions)
- 15:19, 28 June 2019 (diff | hist) . . (0) . . N File:M format.png (current)
- 15:19, 28 June 2019 (diff | hist) . . (+1,414) . . ISA (→M type instructions)
- 15:16, 28 June 2019 (diff | hist) . . (+6) . . ISA (→J type instructions)
- 15:16, 28 June 2019 (diff | hist) . . (0) . . N File:J format.png (current)
- 15:16, 28 June 2019 (diff | hist) . . (+413) . . ISA (→J type instructions)
- 15:15, 28 June 2019 (diff | hist) . . (+6) . . ISA (→C type instructions)
- 15:15, 28 June 2019 (diff | hist) . . (0) . . N File:C format.png (current)
- 15:15, 28 June 2019 (diff | hist) . . (+405) . . ISA (→C type instructions)
- 15:13, 28 June 2019 (diff | hist) . . (-18) . . ISA (→R type instructions)
- 15:13, 28 June 2019 (diff | hist) . . (-18) . . ISA (→I type instructions)
- 15:12, 28 June 2019 (diff | hist) . . (+6) . . ISA (→MOVEI type instructions)
- 15:12, 28 June 2019 (diff | hist) . . (0) . . N File:MOVEI format.png (current)
- 15:12, 28 June 2019 (diff | hist) . . (-10) . . ISA (→MOVEI type instructions)
- 15:11, 28 June 2019 (diff | hist) . . (+518) . . ISA (→MOVEI type instructions)
- 15:05, 28 June 2019 (diff | hist) . . (+6) . . ISA (→I type instructions)
- 15:04, 28 June 2019 (diff | hist) . . (0) . . N File:I instr.png (current)
- 15:04, 28 June 2019 (diff | hist) . . (+639) . . ISA (→I type instructions)
- 14:59, 28 June 2019 (diff | hist) . . (+854) . . ISA (→R type instructions)
- 14:57, 28 June 2019 (diff | hist) . . (+6) . . ISA (→R type instructions)
- 14:57, 28 June 2019 (diff | hist) . . (0) . . N File:RR format.png (current)
- 14:57, 28 June 2019 (diff | hist) . . (+5) . . ISA (→R type instructions)
- 14:56, 28 June 2019 (diff | hist) . . (+91) . . ISA (→R type instructions)
- 14:53, 28 June 2019 (diff | hist) . . (+641) . . ISA
- 14:52, 28 June 2019 (diff | hist) . . (+1) . . Core (→Control registers) (current)
- 15:44, 25 June 2019 (diff | hist) . . (+6) . . Coherence Injection (→Understanding the Testbench) (current)
- 15:43, 25 June 2019 (diff | hist) . . (0) . . N File:Tb coherence injection schema new.jpg (current)
- 15:43, 25 June 2019 (diff | hist) . . (-2) . . Coherence Injection (→Understanding the Testbench)
- 15:43, 25 June 2019 (diff | hist) . . (0) . . File:Tb coherence injection schema.jpg (Mirko uploaded a new version of File:Tb coherence injection schema.jpg) (current)
- 15:34, 25 June 2019 (diff | hist) . . (+13) . . SC Synch (current)
- 15:33, 25 June 2019 (diff | hist) . . (-34) . . SC Synch
- 15:32, 25 June 2019 (diff | hist) . . (-45) . . SC Logger
- 15:31, 25 June 2019 (diff | hist) . . (-35) . . SC Item (current)
- 15:28, 25 June 2019 (diff | hist) . . (-339) . . SC Item
- 15:24, 25 June 2019 (diff | hist) . . (+235) . . SC Item
- 15:21, 25 June 2019 (diff | hist) . . (+312) . . SC Logger
- 15:18, 25 June 2019 (diff | hist) . . (+41) . . SC Item (→Querying Logger)
- 15:17, 25 June 2019 (diff | hist) . . (+13) . . SC System (current)
- 15:16, 25 June 2019 (diff | hist) . . (+104) . . SC System
- 15:13, 25 June 2019 (diff | hist) . . (+4) . . Network interface (→Core to network module)
- 15:11, 25 June 2019 (diff | hist) . . (-13) . . Network interface (→Control unit)
- 14:39, 25 June 2019 (diff | hist) . . (+6) . . Programming Model (→Execution Model Matching)
- 14:39, 25 June 2019 (diff | hist) . . (0) . . N File:Execution model new.png (current)
- 14:38, 25 June 2019 (diff | hist) . . (-1) . . Programming Model (→Execution Model Matching)
- 14:36, 25 June 2019 (diff | hist) . . (0) . . Programming Model (→Memory Model Matching)
- 14:36, 25 June 2019 (diff | hist) . . (0) . . File:Memory mod new.png (Mirko uploaded a new version of File:Memory mod new.png) (current)
- 14:35, 25 June 2019 (diff | hist) . . (-1) . . Programming Model (→Memory Model Matching)
- 14:35, 25 June 2019 (diff | hist) . . (+1) . . Programming Model (→Memory Model Matching)
- 14:34, 25 June 2019 (diff | hist) . . (+6) . . Programming Model (→Memory Model Matching)
- 14:34, 25 June 2019 (diff | hist) . . (0) . . N File:Memory mod new.png
- 14:34, 25 June 2019 (diff | hist) . . (-2) . . Programming Model (→Memory Model Matching)
- 14:33, 25 June 2019 (diff | hist) . . (+6) . . Programming Model (→OpenCL support for NaplesPU)
- 14:33, 25 June 2019 (diff | hist) . . (0) . . N File:Plat model new.png (current)
- 14:32, 25 June 2019 (diff | hist) . . (-2) . . Programming Model (→OpenCL support for NaplesPU)
- 14:32, 25 June 2019 (diff | hist) . . (0) . . File:Plat model.png (Mirko uploaded a new version of File:Plat model.png) (current)
- 14:09, 25 June 2019 (diff | hist) . . (-22) . . Network (→General architecture) (current)
- 13:54, 25 June 2019 (diff | hist) . . (-1) . . MSI Protocol (→The key role of MC_Ack) (current)
- 13:54, 25 June 2019 (diff | hist) . . (-51) . . MSI Protocol (→Limited directory memory)
- 13:52, 25 June 2019 (diff | hist) . . (+306) . . L2 and Directory cache controller (→Message Generator)
- 13:47, 25 June 2019 (diff | hist) . . (+1) . . L2 and Directory cache controller (→Replacement Logic)
- 13:47, 25 June 2019 (diff | hist) . . (-141) . . L2 and Directory cache controller (→Replacement Logic)
- 13:13, 25 June 2019 (diff | hist) . . (-36) . . L2 and Directory cache controller (→Replacement Logic)
- 13:01, 25 June 2019 (diff | hist) . . (-254) . . L2 and Directory cache controller (→Cache Update Logic)
- 12:54, 25 June 2019 (diff | hist) . . (-236) . . L2 and Directory cache controller (→TSHR Update Logic)
- 12:49, 25 June 2019 (diff | hist) . . (+99) . . L2 and Directory cache controller (→Protocol ROM)
- 12:49, 25 June 2019 (diff | hist) . . (+10) . . L2 and Directory cache controller (→Protocol ROM)
- 12:47, 25 June 2019 (diff | hist) . . (+1,691) . . L2 and Directory cache controller (→Stage 3)
- 12:33, 25 June 2019 (diff | hist) . . (-4) . . L2 and Directory cache controller (→Stage 2)
- 12:28, 25 June 2019 (diff | hist) . . (+24) . . L2 and Directory cache controller (→Stage 1)
- 12:19, 25 June 2019 (diff | hist) . . (+2) . . L2 and Directory cache controller (→Stage 1)
- 12:04, 25 June 2019 (diff | hist) . . (+21) . . L2 and Directory cache controller
- 11:58, 25 June 2019 (diff | hist) . . (+13) . . L1 Cache Controller (→Cache Update Logic)
- 11:50, 25 June 2019 (diff | hist) . . (+36) . . L1 Cache Controller (→MSHR Update Logic)
- 11:43, 25 June 2019 (diff | hist) . . (+6) . . L1 Cache Controller (→Replacement Logic)
- 11:40, 25 June 2019 (diff | hist) . . (+3) . . L1 Cache Controller (→Issuing a Request)
- 11:39, 25 June 2019 (diff | hist) . . (-4) . . L1 Cache Controller (→Request Issue Signals)
- 11:39, 25 June 2019 (diff | hist) . . (+358) . . L1 Cache Controller (→Stage 1)
- 11:28, 25 June 2019 (diff | hist) . . (-4) . . L1 Cache Controller (→Assumptions)
- 18:32, 21 June 2019 (diff | hist) . . (-102) . . L1 Cache Controller (→MSHR Update Logic)
- 18:18, 21 June 2019 (diff | hist) . . (+174) . . L1 Cache Controller (→Replacement Logic)
- 18:06, 21 June 2019 (diff | hist) . . (-34) . . L1 Cache Controller (→Protocol ROM)
- 17:20, 21 June 2019 (diff | hist) . . (+83) . . L1 Cache Controller (→Protocol ROM)
- 17:17, 21 June 2019 (diff | hist) . . (+28) . . L1 Cache Controller (→MSHR)
- 17:14, 21 June 2019 (diff | hist) . . (-110) . . L1 Cache Controller (→Hit/miss logic)
- 17:07, 21 June 2019 (diff | hist) . . (+27) . . L1 Cache Controller (→Requests Scheduler)
- 17:05, 21 June 2019 (diff | hist) . . (+2) . . L1 Cache Controller (→Request Issue Signals)
- 17:05, 21 June 2019 (diff | hist) . . (+1) . . L1 Cache Controller (→Request Issue Signals)
- 16:54, 21 June 2019 (diff | hist) . . (+64) . . L1 Cache Controller (→Request Issue Signals)
- 16:48, 21 June 2019 (diff | hist) . . (+377) . . L1 Cache Controller (→Stall Protocol ROMs)
- 16:45, 21 June 2019 (diff | hist) . . (-25) . . L1 Cache Controller (→Stall Protocol ROMs)
- 16:38, 21 June 2019 (diff | hist) . . (+4) . . L1 Cache Controller (→MSHR Signals)
- 16:37, 21 June 2019 (diff | hist) . . (0) . . L1 Cache Controller (→Assumptions)
- 16:36, 21 June 2019 (diff | hist) . . (+3) . . L1 Cache Controller (→Assumptions)
- 16:36, 21 June 2019 (diff | hist) . . (+26) . . L1 Cache Controller
- 16:31, 21 June 2019 (diff | hist) . . (+15) . . MSI Protocol (→The key role of MC_Ack)
- 16:27, 21 June 2019 (diff | hist) . . (+80) . . MSI Protocol (→The key role of MC_Ack)
- 16:07, 21 June 2019 (diff | hist) . . (+24) . . MSI Protocol (→The key role of MC_Ack)
- 16:04, 21 June 2019 (diff | hist) . . (+344) . . MSI Protocol (→Transitions of state N)
- 15:55, 21 June 2019 (diff | hist) . . (-115) . . MSI Protocol (→Limited directory memory)
- 15:49, 21 June 2019 (diff | hist) . . (+27) . . Network interface (→General architecture)
- 15:47, 21 June 2019 (diff | hist) . . (+10) . . Network (→Data structures)
- 15:28, 21 June 2019 (diff | hist) . . (+34) . . MC Item (→Running threads) (current)
- 15:28, 21 June 2019 (diff | hist) . . (+9) . . MC Item (→Setting PCs)
- 15:27, 21 June 2019 (diff | hist) . . (+1) . . MC Item
- 15:25, 21 June 2019 (diff | hist) . . (+7) . . Heterogeneous Tile (→Adding custom logic)
- 15:24, 21 June 2019 (diff | hist) . . (+22) . . Heterogeneous Tile (→Synchronization Interface)
- 15:23, 21 June 2019 (diff | hist) . . (+11) . . Heterogeneous Tile
- 15:21, 21 June 2019 (diff | hist) . . (+18) . . MC System (→H2C tile)
- 15:21, 21 June 2019 (diff | hist) . . (+1) . . MC System (→MC tile)
- 15:21, 21 June 2019 (diff | hist) . . (+8) . . MC System (→MC tile)
- 15:20, 21 June 2019 (diff | hist) . . (+9) . . MC System (→NPU tile)
- 15:19, 21 June 2019 (diff | hist) . . (+41) . . MC System (→NPU tile)
- 15:18, 21 June 2019 (diff | hist) . . (+9) . . MC System (→NPU tile)
- 15:17, 21 June 2019 (diff | hist) . . (+7) . . MC System (→NPU tile)
- 15:15, 21 June 2019 (diff | hist) . . (-1) . . Core (→Result Composer)
- 15:14, 21 June 2019 (diff | hist) . . (+535) . . Core (→Result Composer)
- 15:13, 21 June 2019 (diff | hist) . . (+647) . . Core (→Result Composer)
- 15:10, 21 June 2019 (diff | hist) . . (+1,512) . . Core (→Writeback stage)
- 15:07, 21 June 2019 (diff | hist) . . (+69) . . Core (→Result Composer)
- 14:56, 21 June 2019 (diff | hist) . . (-1) . . Synchronization (→Barrier Synchronization Protocol) (current)
- 14:48, 21 June 2019 (diff | hist) . . (-111) . . Scratchpad unit
- 14:47, 21 June 2019 (diff | hist) . . (+1,821) . . Core (→Control registers)
- 14:27, 21 June 2019 (diff | hist) . . (-15) . . Core (→Cache Pseudo-LRU)
- 14:27, 21 June 2019 (diff | hist) . . (+70) . . Core (→Cache Pseudo-LRU)
- 14:26, 21 June 2019 (diff | hist) . . (+647) . . Core (→Cache Pseudo-LRU)
- 14:21, 21 June 2019 (diff | hist) . . (+26) . . Basic comps (→Memory Banks)
- 14:20, 21 June 2019 (diff | hist) . . (+182) . . Basic comps
- 14:15, 21 June 2019 (diff | hist) . . (0) . . Include (→Synchronization Defines)
- 14:15, 21 June 2019 (diff | hist) . . (+36) . . Include (→Synchronization Defines)
- 14:14, 21 June 2019 (diff | hist) . . (+50) . . Include (→Scratchpad Memory Defines)
- 14:13, 21 June 2019 (diff | hist) . . (+16) . . Include (→User Defines)
- 14:13, 21 June 2019 (diff | hist) . . (+27) . . Include (→NPU Defines)
- 14:12, 21 June 2019 (diff | hist) . . (+12) . . Include (→Coherence Defines)
- 14:11, 21 June 2019 (diff | hist) . . (+5) . . Include (→Synchronization Defines)
- 14:10, 21 June 2019 (diff | hist) . . (+24) . . Include (→Network Defines)
- 14:09, 21 June 2019 (diff | hist) . . (+5) . . Include (→Scratchpad Memory Defines)
- 14:08, 21 June 2019 (diff | hist) . . (-20) . . Include (→NPU Defines)
- 14:07, 21 June 2019 (diff | hist) . . (+38) . . Include (→User Defines)
- 14:06, 21 June 2019 (diff | hist) . . (+11) . . Include
- 14:04, 21 June 2019 (diff | hist) . . (0) . . The NaplesPU Hardware architecture (→Tile Overview)
- 14:01, 21 June 2019 (diff | hist) . . (-1) . . Main Page (→simulate.sh script)
- 14:00, 21 June 2019 (diff | hist) . . (-1) . . Main Page (→setup_project.sh script)
- 13:57, 21 June 2019 (diff | hist) . . (-6) . . Main Page (→Getting started)
- 17:04, 20 June 2019 (diff | hist) . . (-44) . . MSI Protocol
- 16:58, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . N File:MSI Protocol dc-rom new.png (current)
- 16:57, 20 June 2019 (diff | hist) . . (-3) . . MSI Protocol (→Directory Controller)
- 15:38, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:38, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:37, 20 June 2019 (diff | hist) . . (0) . . File:MSI Protocol cc-rom p2 new.png (Mirko uploaded a new version of File:MSI Protocol cc-rom p2 new.png) (current)
- 15:37, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Cache Controller)
- 15:36, 20 June 2019 (diff | hist) . . (0) . . N File:MSI Protocol cc-rom p2 new.png
- 15:36, 20 June 2019 (diff | hist) . . (-3) . . MSI Protocol (→Cache Controller)
- 15:32, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:32, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Cache Controller)
- 15:32, 20 June 2019 (diff | hist) . . (0) . . N File:MSI Protocol cc-rom p1 new.png (current)
- 15:32, 20 June 2019 (diff | hist) . . (-3) . . MSI Protocol (→Cache Controller)
- 13:38, 20 June 2019 (diff | hist) . . (-2) . . ISA (→Instructions Format)
- 13:38, 20 June 2019 (diff | hist) . . (-117) . . ISA (→Register File)
- 13:37, 20 June 2019 (diff | hist) . . (+118) . . ISA (→Register File)
- 13:37, 20 June 2019 (diff | hist) . . (-118) . . ISA (→Register File)
- 13:37, 20 June 2019 (diff | hist) . . (-546) . . ISA (→M type instructions)
- 13:34, 20 June 2019 (diff | hist) . . (0) . . N File:ScalarRegFile new.png (current)
- 13:34, 20 June 2019 (diff | hist) . . (0) . . N File:VectorRegFile new.png (current)
- 13:34, 20 June 2019 (diff | hist) . . (+8) . . ISA (→Register File)
- 13:32, 20 June 2019 (diff | hist) . . (0) . . File:ScalarRegFile.png (Mirko uploaded a new version of File:ScalarRegFile.png) (current)
- 13:27, 20 June 2019 (diff | hist) . . (-329) . . ISA (→Register File)
- 13:09, 20 June 2019 (diff | hist) . . (+74) . . ISA (→C type instructions)
- 13:07, 20 June 2019 (diff | hist) . . (-90) . . ISA (→R type instructions)
- 13:05, 20 June 2019 (diff | hist) . . (-2) . . ISA (→R type instructions)
- 13:05, 20 June 2019 (diff | hist) . . (+59) . . ISA (→R type instructions)
- 13:00, 20 June 2019 (diff | hist) . . (-22) . . ISA
- 15:41, 19 June 2019 (diff | hist) . . (-2) . . NaplesPU Clang Documentation
- 15:40, 19 June 2019 (diff | hist) . . (0) . . m NaplesPU Clang Documentation (Mirko moved page Nu+ Clang Documentation to NaplesPU Clang Documentation)
- 15:40, 19 June 2019 (diff | hist) . . (+42) . . N Nu+ Clang Documentation (Mirko moved page Nu+ Clang Documentation to NaplesPU Clang Documentation) (current)
- 15:40, 19 June 2019 (diff | hist) . . (+99) . . Toolchain
- 15:38, 19 June 2019 (diff | hist) . . (-52) . . Main Page (→Documentation)
- 15:36, 19 June 2019 (diff | hist) . . (-18) . . Programming Model (→NaplesPU Misc Intrinsics)
- 15:36, 19 June 2019 (diff | hist) . . (0) . . N File:NPU Intr.png (current)
- 15:36, 19 June 2019 (diff | hist) . . (+22) . . Programming Model (→NaplesPU Misc Intrinsics)
- 15:33, 19 June 2019 (diff | hist) . . (+5) . . Programming Model
- 15:32, 19 June 2019 (diff | hist) . . (-14) . . Programming Model
- 15:27, 19 June 2019 (diff | hist) . . (-10) . . Extending NaplesPU
- 15:24, 19 June 2019 (diff | hist) . . (0) . . m Extending NaplesPU (Mirko moved page Extending nu+ to Extending NaplesPU)
- 15:24, 19 June 2019 (diff | hist) . . (+32) . . N Extending nu+ (Mirko moved page Extending nu+ to Extending NaplesPU) (current)
- 15:23, 19 June 2019 (diff | hist) . . (+25) . . Main Page (→Documentation)
- 15:23, 19 June 2019 (diff | hist) . . (-651) . . Main Page
- 15:07, 19 June 2019 (diff | hist) . . (+26) . . Main Page
- 15:06, 19 June 2019 (diff | hist) . . (-61) . . Coherence Injection
- 15:00, 19 June 2019 (diff | hist) . . (-25) . . System deployment (current)
- 15:00, 19 June 2019 (diff | hist) . . (0) . . N File:NPU nexys4.png (current)
- 14:59, 19 June 2019 (diff | hist) . . (+25) . . System deployment
- 14:59, 19 June 2019 (diff | hist) . . (-10) . . System deployment
- 14:56, 19 June 2019 (diff | hist) . . (+2) . . SC Logger
- 14:55, 19 June 2019 (diff | hist) . . (-7) . . SC Synch
- 14:54, 19 June 2019 (diff | hist) . . (+11) . . Single Core Cache Controller (current)
- 14:52, 19 June 2019 (diff | hist) . . (-4) . . SC Item
- 14:52, 19 June 2019 (diff | hist) . . (+25) . . SC System
- 14:51, 19 June 2019 (diff | hist) . . (-72) . . SC System
- 14:51, 19 June 2019 (diff | hist) . . (0) . . N File:NPU sc system.png (current)
- 14:51, 19 June 2019 (diff | hist) . . (+70) . . SC System
- 14:48, 19 June 2019 (diff | hist) . . (+4) . . The NaplesPU Hardware architecture
- 14:47, 19 June 2019 (diff | hist) . . (-291) . . Network router
- 14:46, 19 June 2019 (diff | hist) . . (0) . . File:First stage.jpg (Mirko uploaded a new version of File:First stage.jpg) (current)
- 14:43, 19 June 2019 (diff | hist) . . (+21) . . Network
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