User contributions
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- 15:21, 21 June 2019 (diff | hist) . . (+1) . . MC System (→MC tile)
- 15:21, 21 June 2019 (diff | hist) . . (+8) . . MC System (→MC tile)
- 15:20, 21 June 2019 (diff | hist) . . (+9) . . MC System (→NPU tile)
- 15:19, 21 June 2019 (diff | hist) . . (+41) . . MC System (→NPU tile)
- 15:18, 21 June 2019 (diff | hist) . . (+9) . . MC System (→NPU tile)
- 15:17, 21 June 2019 (diff | hist) . . (+7) . . MC System (→NPU tile)
- 15:15, 21 June 2019 (diff | hist) . . (-1) . . Core (→Result Composer)
- 15:14, 21 June 2019 (diff | hist) . . (+535) . . Core (→Result Composer)
- 15:13, 21 June 2019 (diff | hist) . . (+647) . . Core (→Result Composer)
- 15:10, 21 June 2019 (diff | hist) . . (+1,512) . . Core (→Writeback stage)
- 15:07, 21 June 2019 (diff | hist) . . (+69) . . Core (→Result Composer)
- 14:56, 21 June 2019 (diff | hist) . . (-1) . . Synchronization (→Barrier Synchronization Protocol) (current)
- 14:48, 21 June 2019 (diff | hist) . . (-111) . . Scratchpad unit
- 14:47, 21 June 2019 (diff | hist) . . (+1,821) . . Core (→Control registers)
- 14:27, 21 June 2019 (diff | hist) . . (-15) . . Core (→Cache Pseudo-LRU)
- 14:27, 21 June 2019 (diff | hist) . . (+70) . . Core (→Cache Pseudo-LRU)
- 14:26, 21 June 2019 (diff | hist) . . (+647) . . Core (→Cache Pseudo-LRU)
- 14:21, 21 June 2019 (diff | hist) . . (+26) . . Basic comps (→Memory Banks)
- 14:20, 21 June 2019 (diff | hist) . . (+182) . . Basic comps
- 14:15, 21 June 2019 (diff | hist) . . (0) . . Include (→Synchronization Defines)
- 14:15, 21 June 2019 (diff | hist) . . (+36) . . Include (→Synchronization Defines)
- 14:14, 21 June 2019 (diff | hist) . . (+50) . . Include (→Scratchpad Memory Defines)
- 14:13, 21 June 2019 (diff | hist) . . (+16) . . Include (→User Defines)
- 14:13, 21 June 2019 (diff | hist) . . (+27) . . Include (→NPU Defines)
- 14:12, 21 June 2019 (diff | hist) . . (+12) . . Include (→Coherence Defines)
- 14:11, 21 June 2019 (diff | hist) . . (+5) . . Include (→Synchronization Defines)
- 14:10, 21 June 2019 (diff | hist) . . (+24) . . Include (→Network Defines)
- 14:09, 21 June 2019 (diff | hist) . . (+5) . . Include (→Scratchpad Memory Defines)
- 14:08, 21 June 2019 (diff | hist) . . (-20) . . Include (→NPU Defines)
- 14:07, 21 June 2019 (diff | hist) . . (+38) . . Include (→User Defines)
- 14:06, 21 June 2019 (diff | hist) . . (+11) . . Include
- 14:04, 21 June 2019 (diff | hist) . . (0) . . The NaplesPU Hardware architecture (→Tile Overview)
- 14:01, 21 June 2019 (diff | hist) . . (-1) . . Main Page (→simulate.sh script)
- 14:00, 21 June 2019 (diff | hist) . . (-1) . . Main Page (→setup_project.sh script)
- 13:57, 21 June 2019 (diff | hist) . . (-6) . . Main Page (→Getting started)
- 17:04, 20 June 2019 (diff | hist) . . (-44) . . MSI Protocol
- 16:58, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Directory Controller)
- 16:57, 20 June 2019 (diff | hist) . . (0) . . N File:MSI Protocol dc-rom new.png (current)
- 16:57, 20 June 2019 (diff | hist) . . (-3) . . MSI Protocol (→Directory Controller)
- 15:38, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:38, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:37, 20 June 2019 (diff | hist) . . (0) . . File:MSI Protocol cc-rom p2 new.png (Mirko uploaded a new version of File:MSI Protocol cc-rom p2 new.png) (current)
- 15:37, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Cache Controller)
- 15:36, 20 June 2019 (diff | hist) . . (0) . . N File:MSI Protocol cc-rom p2 new.png
- 15:36, 20 June 2019 (diff | hist) . . (-3) . . MSI Protocol (→Cache Controller)
- 15:32, 20 June 2019 (diff | hist) . . (0) . . MSI Protocol (→Cache Controller)
- 15:32, 20 June 2019 (diff | hist) . . (+7) . . MSI Protocol (→Cache Controller)
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