NaplesPU Documentation - User contributions [en]

Extending NaplesPU for OpenCL support

2019-06-21T15:24:27Z

Francesco:

This section describes how the OpenCL C kernel compilation is supported in the NaplesPU toolchain.
Since Clang natively supports the IR generation of OpenCL C kernels, our work focused on the adaption of the generated code on the NaplesPU core. As the NaplesPU start routine requires to jump to the ''main'' label after having initialized all necessary resources, it is necessary to build a custom optimization pass, to auto-generate the main-function and to define the calling frame to the kernel function. Also OpenCL requires the implementation of custom libraries, extending the ''libc'' set.

== LLVM IR Optimization ==

An IR optimization can be of two different types:
* Analysis, does not provide a modification of the intermediate representation;
* Transform, produces a modified IR as output.

LLVM provides an API to create a new optimization pass, hierarchically implemented on the ''Pass'' Class from which the following ones inherit:
* ModulePass: it is the most general pass. It allows the whole module and the function of which it is composed to be checked.
* FunctionPass: it allows functions defined in all modules (except for the external ones) to be managed without pursuing a specific order. Functions cannot be deleted.
* BasicBlockPass: it allows basic blocks to be managed. A basic block can be modified but not removed.

As a consequence of the classification provided above, for our purpose, the definition of a ModulePass is the most suitable choice.

To write a custom module pass, it is necessary to define a new class by inheriting the ModulePass one and overriding the ''runOnModule()'' method. It contains the code that is executed at each LLVM per-module optimization. If the defined pass modifies the IR, the ''runOnModule'' function returns a ''true'' value. Otherwise, it returns a ''false'' value. As previously discussed, the custom pass should create the ''main'' function by parsing the arguments from the ''argv'' field, and then by calling the kernel function with the right parameters.

The generated code should be of the form as described below.
<syntaxhighlight>
; Function Attrs: nounwind
define void @main(i32, i8** nocapture readonly) local_unnamed_addr #0 {
%3 = bitcast i8** %1 to i32*
%4 = load i32, i32* %3, align 4
...
tail call void @kernel_f(i32 %4, ...) #2
ret void
}
</syntaxhighlight>

As a consequence, the ModulePass should be structured in the following points:

* Definition of the main function signature:
<syntaxhighlight>
FunctionType *main_type =
TypeBuilder<void(int, char**), false>::get(ctx);
Function *func =
cast<Function>(M.getOrInsertFunction("main", main_type));
</syntaxhighlight>

*Creation of an ''entry'' labeled basic block:
<syntaxhighlight>
BasicBlock *block = BasicBlock::Create(ctx, "entry", func, 0);
builder.SetInsertPoint(block);
</syntaxhighlight>

* For each kernel argument, create an aligned load instruction to retrieve the argument from the ''argv'' array and add it to the kernel arguments:
<syntaxhighlight>
argument_list[counter] = builder.CreateLoad(arg.getType(),
builder.CreateBitCast(builder.CreateGEP(&argv,
builder.getInt32(index)),
arg.getType()->getPointerTo()));
argument_list[counter]->setAlignment(4);
kernel_arguments.push_back(argument_list[counter++]);
</syntaxhighlight>

*Kernel function call:
<syntaxhighlight>
builder.CreateCall(kernel_function, kernel_arguments);
</syntaxhighlight>

Once the pass is defined, the next step consists to register the pass in the ''PassManager'' to add it to the IR optimization pipeline.
LLVM provides a set of macros that are to be used to initialize the pass:

<syntaxhighlight>
INITIALIZE_PASS_BEGIN(...)
INITIALIZE_PASS_END(...)
</syntaxhighlight>

and to define the pass dependencies:
<syntaxhighlight>
INITIALIZE_PASS_DEPENDENCIES(...)
</syntaxhighlight>

The pass initialization must be linked through the ''InitializePasses.h'' header file, in which the following function has to be defined:
<syntaxhighlight>
void initialize<PassName>Pass(PassRegistry &);
</syntaxhighlight>

In addition, the specific ModulePass constructor must be declared in the ''LinkAllPasses.h'' header file.

By following these steps, the optimization pass created is automatically chained to the ''opt'' tool pipeline. Moreover, it is useful to automatically execute the pass in each ''clang'' compilation. In order to realize the desired behaviour, the code generation step has to be modified. Clang provides the ''EmitAssemblyHelper::CreatePasses'' method to add a pass to the [[PassManager]].

As an example, consider the following trivial OpenCL kernel:

<syntaxhighlight>
__kernel void kernel_function(unsigned param,
__global unsigned* out)
{

unsigned int i = 0;
*out = i + param;

}
</syntaxhighlight>

The optimization pass creates the main function as follows:
<syntaxhighlight>
define void @main(i32, i8** nocapture readonly) local_unnamed_addr #1 {
entry:
%2 = getelementptr i8*, i8** %1, i64 6
%3 = bitcast i8** %2 to i32*
%4 = load i32, i32* %3, align 4
%5 = getelementptr i8*, i8** %1, i64 7
%6 = bitcast i8** %5 to i32**
%7 = load i32*, i32** %6, align 4
tail call void @kernel_function(i32 %4, i32* %7)
ret void
}
</syntaxhighlight>

As a result, the NaplesPU processor is now capable to run OpenCL kernels.

== Library Extensions ==
OpenCL provides a set of vector types to explicitly support the lock-step execution. Since NaplesPU is internally structured in a set of hardware lanes, the natively supported vector types are the following:

* ''char16'', ''uchar16'' are respectively mapped on ''vec16i8'' and ''vec16u8'';
* ''short16'' , ''ushort16'' are respectively mapped on ''vec16i16'' and ''vec16i32''
* ''int16'', ''uint16'' are respectively mapped on ''vec16i32'' and ''vec16u32'';
* ''float16'' is mapped on ''vec16f32''.

The OpenCL support for these vector types is provided by adapting the compiler standard library. The adaption involves the modification of the stdint.h library, by adding the lines below.

<syntaxhighlight>
typedef char char16 __attribute__((ext_vector_type(16)));
typedef unsigned char uchar16 __attribute__((ext_vector_type(16)));
typedef short short16 __attribute__((ext_vector_type(16)));
typedef unsigned short ushort16 __attribute__((ext_vector_type(16)));
typedef int int16 __attribute__((ext_vector_type(16)));
typedef unsigned int uint16 __attribute__((ext_vector_type(16)));
typedef float float16 __attribute__((ext_vector_type(16)));
</syntaxhighlight>

OpenCL supports a set of builtins used by work-items to retrieve several pieces of information about the enqueued kernel, such as work-item local and global IDs, index space sizes and so on.
The implementation of these functions relies on the target builtins to obtain information stored on platform registers.
For instance, take a look to the following code.

<syntaxhighlight>
#define WORK_DIM 1

uint get_work_dim () {
return WORK_DIM;
}

uint get_local_id(uint dimindx){
return __builtin_NaplesPU_read_control_reg(LOCAL_ID);
}

uint get_global_id(uint dimindx){
return __builtin_NaplesPU_read_control_reg(GLOBAL_ID);
}

uint get_group_id(uint dimindx){
return __builtin_NaplesPU_read_control_reg(CORE_ID);
}
</syntaxhighlight>

As it is exposed, the work-item builtins implementation maps on NaplesPU builtins, in order to read the control register containing the desired value. Also take note of the WORK_DIM macro, statically defined as 1, because of the hardware constraints.

Extending NaplesPU for 64-bit support

2019-06-21T15:23:30Z

Francesco:

NaplesPU toolchain can be extended to support 64-bit operations.
A git branch with full 64-bit support is provided. Consequently, if it is necessary to compile the toolchain supporting this extension, a ''checkout'' on ''llvm-7-64b'' branch is required.

Changes are related to both [[NaplesPU Clang Documentation | frontend]] and [[NaplesPU LLVM Documentation | backend]].

== NaplesPU Frontend Modifications ==

NaplesPU frontend abstracts target informations through the ''TargetInfo'' class, extending it in the [[NaplesPU Clang Documentation #Defining Target Features | NaplesPUTargetInfo]] implementation.

Since 64-bit operations require to support double-integer and double-floating-point formats, the following changes and additions are required in the target definition:

<syntaxhighlight>
class LLVM_LIBRARY_VISIBILITY NaplesPUTargetInfo : public TargetInfo {
...
public:
NaplesPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
: TargetInfo(Triple) {
...
resetDataLayout("e-m:e-p:32:32-i64:64:64-i32:32:32-f32:32:32-f64:64:64");
LongDoubleWidth = 64;
LongDoubleAlign = 64;
DoubleWidth = 64;
DoubleAlign = 64;
LongWidth = 64;
LongAlign = 64;
LongLongWidth = 64;
LongLongAlign = 64;
}
</syntaxhighlight>

== NaplesPU Backend Modifications ==

This section describes the backend modification to be applied for 64-bit support.

=== Registers Definition ===
The 64-bit support for registers is based on the "Sub-Reg" behaviour. Since NaplesPU registers are 32-bit wide, a 64-bit variable is stored split in two parts:
* The higher 32-bit are placed in the S[i] register;
* The lower 32-bit are placed in the S[i+1] register.

The following class is declared in [[NaplesPURegisterInfo.td]].

<syntaxhighlight>
class NaplesPU64GPRReg<bits<16> Enc, string n, list<Register> subregs>
: NaplesPURegWithSubRegs<Enc, n, subregs> {
let SubRegIndices = [sub_even, sub_odd];
let CoveredBySubRegs = 1;
}
</syntaxhighlight>

The register instantiation is realized as follows:
<syntaxhighlight>
foreach i = 0-28 in {
def S#!shl(i, 1)#_S#!add(!shl(i, 1), 1) : NaplesPU64GPRReg<!shl(i, 1), "s"#!shl(i, 1)#_64,
[!cast<NaplesPUGPRReg>("S"#!shl(i, 1)),
!cast<NaplesPUGPRReg>("S"#!add(!shl(i, 1), 1))]>;
}
</syntaxhighlight>

Using the newly defined 64-bit support, it is possible to manage vector registers partitioned in eight cells, in which each one is 64-bit wide.

<syntaxhighlight>
def VR512L : RegisterClass<"NaplesPU", [v8i64, v8f64, v8i8, v8i16, v8i32], 512, (sequence "V%u", 0, 63)>;
</syntaxhighlight>

=== Calling Convention ===
Calling conventions for NaplesPU are modified supporting the 64-bit registers. As a result, the [[NaplesPU LLVM Documentation #Calling Convention | 32-bit Calling Convention]] is extended by adding the following lines:

<syntaxhighlight>
CCIfType<[v8i8, v8i16, v8i32], CCPromoteToType<v8i64>>,

CCIfNotVarArg<CCIfType<[i64, f64], CCAssignToReg<[S0_S1, S2_S3, S4_S5, S6_S7, S8_S9, S10_S11, S12_S13, S14_S15]>>>,

CCIfNotVarArg<CCIfType<[v16i32, v16f32, v8i64, v8f64], CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>>,
</syntaxhighlight>

The lines above describes how parameters are passed through registers. Also the stack assignment is described below:

<syntaxhighlight>
CCIfType<[i64, f64], CCAssignToStack<8, 8>>,
CCIfType<[v16i32, v16f32, v8i64, v8f64], CCAssignToStack<64, 64>>
</syntaxhighlight>

The return value calling convention is extended follows:

<syntaxhighlight>
CCIfType<[i64, f64], CCAssignToReg<[S0_S1, S2_S3, S4_S5, S6_S7, S8_S9, S10_S11]>>,
CCIfType<[v8i8, v8i16, v8i32], CCPromoteToType<v8i64>>,
CCIfType<[v16i32, v16f32, v8i64, v8f64], CCAssignToReg<[V0, V1, V2, V3, V4, V5]>>
</syntaxhighlight>

=== ISA Support ===

Referring to [[NaplesPU LLVM Documentation #ISA Support | 32-bit ISA Support]] the 64-bit support on instructions is realized by extending the NaplesPU instruction hierarchy, adding a bit that acts as a mark.

As an example, in the following code, the bit <FR_TwoOp_Unmasked_64> class is derived from the <FR_TwoOp_Unmasked>, setting the sixth parameter as <1>. Recalling what described in the [[NaplesPU LLVM Documentation #ISA Support | 32-bit ISA Support]], it describes if the instruction refers to a 64-bit behaviour or not.

<syntaxhighlight>
class FR_TwoOp_Unmasked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Unmasked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1, fmt0> {}
</syntaxhighlight>

=== Instruction Lowering ===
Since new instructions are defined, a ''lowering'' behaviour on them is often required. As a result, [[NaplesPUISelLowering.cpp | NaplesPUISelLowering]] is extended in some points. For instance, since ''LoadI64'' is a pseudo-instruction, it must be expanded as follows:
<syntaxhighlight>
case NaplesPU::LoadI64:
return EmitLoadI64(&MI, BB);
...
MachineBasicBlock *
NaplesPUTargetLowering::EmitLoadI64(MachineInstr *MI,
MachineBasicBlock *BB) const {

DebugLoc DL = MI->getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();

// Create the destination register
unsigned DstReg = MI->getOperand(0).getReg();
int64_t ImmOp = MI->getOperand(1).getImm();

unsigned Immediate = ((ImmOp >> 32) & 0xffffffff);

BuildMI(*BB, MI, DL, TII->get(NaplesPU::MOVEIHSI))
.addReg(DstReg, RegState::Define, NaplesPU::sub_odd)
.addImm(((Immediate >> 16) & 0xFFFF));
BuildMI(*BB, MI, DL, TII->get(NaplesPU::MOVEILSI))
.addReg(DstReg, 0, NaplesPU::sub_odd)
.addImm((Immediate & 0xFFFF));

Immediate = (ImmOp & 0xffffffff);

BuildMI(*BB, MI, DL, TII->get(NaplesPU::MOVEIHSI))
.addReg(DstReg, 0, NaplesPU::sub_even)
.addImm(((Immediate >> 16) & 0xFFFF));
BuildMI(*BB, MI, DL, TII->get(NaplesPU::MOVEILSI))
.addReg(DstReg, 0, NaplesPU::sub_even)
.addImm((Immediate & 0xFFFF));

MI->eraseFromParent();

return BB;
}
</syntaxhighlight>
As it is explained, the load operation for 64-bit immediate value is realized by requiring a ''NaplesPU64GPR'' register and writing the split parts on the sub-registers.

=== Disassembler Support ===
Since new register classes are introduced, proper decode methods are implemented in '''NaplesPUDisassembler'''. As a result, ''DecodeGPR64RegisterClasses'' and ''DecodeVR512LRegisterClasses'' are added to disassemble the code.

NaplesPU Libraries

2019-06-21T15:22:50Z

Francesco:

NaplesPU is provided with different kind of libraries that are contained in the libs/ folder.

== libc ==
We implemented our custom version of the following standard C libraries:
* ctype
* math
* stdlib
* string

Note that these libraries are not fully developed and, hence, some functions may be missing. In particular, dynamic memory management (calloc, free, malloc, realloc) and environment (abort, atexit, at_quick_exit, exit, getenv, quick_exit, system) functions are not implemented. In addition, we redefined the stdint.h header file in order to provide a set of typedefs that specify vector types.

During compilation, these libraries are archived together into a single file, i.e. libc.a, using the llvm-ar archiver.

== libcompiler ==
This folder contains the libraries that are required by the compiler to handle some arithmetic operations that are not legal in the target architecture. In particular, we implemented the following libraries:
* divdi3.c: signed 64-bit integer division
* divsi3.c: signed 32-bit integer division
* moddi3.c: signed 64-bit integer modulus
* modsi3.c: signed 32-bit integer modulus
* udivdi3.c: unsigned 64-bit integer division
* udivsi3.c: unsigned 32-bit integer division
* umoddi3.c: unsigned 64-bit integer modulus
* umodsi3.c: unsigned 32-bit integer modulus
A proper lib call is generated when lowering the following node types:
*ISD::UDIV
*ISD::UREM
*ISD::SDIV
*ISD::SREM
This happends because the setOperationAction for the above nodes are set to ''Expand'' inside the [[NaplesPUISelLowering_class | NaplesPUISelLowering.cpp]] file.

== isr==
This folder contains the NaplesPU Interrupt Service Routines (ISRs). In the current version we have just a single isr, i.e. isr0, which implements an endless loop.

== vectors.s ==
This assembler file contains the Interrupt Vector Jump Table. Jump operations to the different ISRs are stored in consecutive 32-bit locations. Since, in the current version we have just a single isr, there is only one jump operations.

== crt0.s ==
This file contains a set of execution startup routines that performs any initialization work required before calling the program's main function. The main steps are:
# Loading the stack/frame pointers from the stack table that is located at the end of the file. The stack table is filled with the addresses of the different stacks that are defined inside the [[LinkerScript | linker script]]. The current version supports eight threads for each core. The offset inside the stack_table is calculated as i*32+j*4, where ''i'' is the core ID and j is the thread ID. In case of an higher number of threads, it is required to change both the crt0.o and the [[LinkerScript | linker script]].
# Thread 0 of Core 0 performs constructor startup required for the initialization of C/C++ objects. This is done by calling the functions that are located inside the .init_array section.
# Threads 0 of each core performs scratchpad preload initialization. This is done using first vector loads/stores, then 64-bit scalar loads/stores and finally 32-bit scalar loads/stores.
# The argc and argv arguments are put inside the s0 and s1 registers according to the NaplesPU [[NaplesPUCallingConv.td | calling convention]].
# All hardware lanes are enabled by default.

NaplesPU Libraries

2019-06-21T15:22:31Z

Francesco:

NuPlus is provided with different kind of libraries that are contained in the libs/ folder.

== libc ==
We implemented our custom version of the following standard C libraries:
* ctype
* math
* stdlib
* string

Note that these libraries are not fully developed and, hence, some functions may be missing. In particular, dynamic memory management (calloc, free, malloc, realloc) and environment (abort, atexit, at_quick_exit, exit, getenv, quick_exit, system) functions are not implemented. In addition, we redefined the stdint.h header file in order to provide a set of typedefs that specify vector types.

During compilation, these libraries are archived together into a single file, i.e. libc.a, using the llvm-ar archiver.

== libcompiler ==
This folder contains the libraries that are required by the compiler to handle some arithmetic operations that are not legal in the target architecture. In particular, we implemented the following libraries:
* divdi3.c: signed 64-bit integer division
* divsi3.c: signed 32-bit integer division
* moddi3.c: signed 64-bit integer modulus
* modsi3.c: signed 32-bit integer modulus
* udivdi3.c: unsigned 64-bit integer division
* udivsi3.c: unsigned 32-bit integer division
* umoddi3.c: unsigned 64-bit integer modulus
* umodsi3.c: unsigned 32-bit integer modulus
A proper lib call is generated when lowering the following node types:
*ISD::UDIV
*ISD::UREM
*ISD::SDIV
*ISD::SREM
This happends because the setOperationAction for the above nodes are set to ''Expand'' inside the [[NuPlusISelLowering_class | NuPlusISelLowering.cpp]] file.

== isr==
This folder contains the nu+ Interrupt Service Routines (ISRs). In the current version we have just a single isr, i.e. isr0, which implements an endless loop.

== vectors.s ==
This assembler file contains the Interrupt Vector Jump Table. Jump operations to the different ISRs are stored in consecutive 32-bit locations. Since, in the current version we have just a single isr, there is only one jump operations.

== crt0.s ==
This file contains a set of execution startup routines that performs any initialization work required before calling the program's main function. The main steps are:
# Loading the stack/frame pointers from the stack table that is located at the end of the file. The stack table is filled with the addresses of the different stacks that are defined inside the [[LinkerScript | linker script]]. The current version supports eight threads for each core. The offset inside the stack_table is calculated as i*32+j*4, where ''i'' is the core ID and j is the thread ID. In case of an higher number of threads, it is required to change both the crt0.o and the [[LinkerScript | linker script]].
# Thread 0 of Core 0 performs constructor startup required for the initialization of C/C++ objects. This is done by calling the functions that are located inside the .init_array section.
# Threads 0 of each core performs scratchpad preload initialization. This is done using first vector loads/stores, then 64-bit scalar loads/stores and finally 32-bit scalar loads/stores.
# The argc and argv arguments are put inside the s0 and s1 registers according to the nu+ [[NuPlusCallingConv.td | calling convention]].
# All hardware lanes are enabled by default.

NaplesPU Libraries

2019-06-21T15:22:26Z

Francesco:

NaplesPU Libraries

2019-06-21T15:22:09Z

Francesco: Francesco moved page Nu+ Libraries to NaplesPU Libraries

Nu+ Libraries

2019-06-21T15:22:09Z

Francesco: Francesco moved page Nu+ Libraries to NaplesPU Libraries

#REDIRECT [[NaplesPU Libraries]]

NaplesPU Tools

2019-06-21T15:22:01Z

Francesco:

NaplesPU is provided with a set of additional tools in order to fully support the compilation process of an application.

== elf2hex ==
elf2hex is the tool required for elf code transformation. It works on an input ELF code to produce a hex output file as the memory image to be written on device memory. NaplesPU relies on its own implementation of the elf2hex tool, located in elf2hex.cpp. In our purposes, the tool produces two different outputs:
* MANGO compliant memory image, a 512-bit little-endian aligned image ready to be flashed on the MANGO platform;
* Standalone compliant memory image, a 512-bit little-endian aligned image to be used in a standalone environment.

== Disassembler ==
A disassembler attempts to revert back the assembly code from the binary one. In order to be able to support NaplesPU code disassembly, LLVM requires to implement a Disassembler class. The implementation is provided in [[NaplesPUDisassembler.cpp]]. Disassembly methods rely on auto-generated ''decoder tables'' from TableGen files. TableGen also offers a way to force a specific decoder method to be called, specifying the ''DecoderMethod'' field on instructions.

<syntaxhighlight>
def V16MEMri : Operand<v16i32> {
let EncoderMethod = "encodeMemoryOpValue";
let DecoderMethod = "decodeVectorWMemoryOpValue";
...
}

static DecodeStatus decodeVectorWMemoryOpValue(...)
{
return decodeMemoryOpValue(Inst, Insn, Address, Decoder,
NaplesPU::VR512WRegClassID);
}
</syntaxhighlight>

== Object File Dumper ==
LLVM provides a custom tool to work as an object file dumper, that is a utility that prints the contents of object files and of the final linked image. For this reason, it is primarily used to debug the generated machine code. In the LLVM implementation, the ''llvm-objdump'' binary relies on the Disassembler classes, in order to revert the binary code into the assembly back.

Nu+ Tools

2019-06-21T15:21:35Z

Francesco: Francesco moved page Nu+ Tools to NaplesPU Tools

#REDIRECT [[NaplesPU Tools]]

NaplesPU Tools

2019-06-21T15:21:35Z

Francesco: Francesco moved page Nu+ Tools to NaplesPU Tools

nu+ is provided with a set of additional tools in order to fully support the compilation process of an application.

== elf2hex ==
elf2hex is the tool required for elf code transformation. It works on an input ELF code to produce a hex output file as the memory image to be written on device memory. nu+ relies on its own implementation of the elf2hex tool, located in elf2hex.cpp. In our purposes, the tool produces two different outputs:
* MANGO compliant memory image, a 512-bit little-endian aligned image ready to be flashed on the MANGO platform;
* Standalone compliant memory image, a 512-bit little-endian aligned image to be used in a standalone environment.

== Disassembler ==
A disassembler attempts to revert back the assembly code from the binary one. In order to be able to support nu+ code disassembly, LLVM requires to implement a Disassembler class. The implementation is provided in [[NuPlusDisassembler.cpp]]. Disassembly methods rely on auto-generated ''decoder tables'' from TableGen files. TableGen also offers a way to force a specific decoder method to be called, specifying the ''DecoderMethod'' field on instructions.

<syntaxhighlight>
def V16MEMri : Operand<v16i32> {
let EncoderMethod = "encodeMemoryOpValue";
let DecoderMethod = "decodeVectorWMemoryOpValue";
...
}

static DecodeStatus decodeVectorWMemoryOpValue(...)
{
return decodeMemoryOpValue(Inst, Insn, Address, Decoder,
NuPlus::VR512WRegClassID);
}
</syntaxhighlight>

== Object File Dumper ==
LLVM provides a custom tool to work as an object file dumper, that is a utility that prints the contents of object files and of the final linked image. For this reason, it is primarily used to debug the generated machine code. In the LLVM implementation, the ''llvm-objdump'' binary relies on the Disassembler classes, in order to revert the binary code into the assembly back.

NaplesPU LLD Linker

2019-06-21T15:21:17Z

Francesco:

LLD is the LLVM proprietary linker. It is based on the GNU linker, and it is compatible to it in terms of arguments accepted. It also fully supports the ''ELF'' generation but also, in a progressive lower percentage, ''PE/COFF'', ''Mach-O'', ''WebAssembly'' and custom linker-scripts.
LLD is built as a set of libraries to join the main idea of the software modular design.

The NaplesPU implementation of LLD is made on an ELF-based approach, by adding a new Target class inside lld/ELF/Arch folder. [[NaplesPU.cpp]] contains the ''relocation'' logic and other information needed to support NaplesPU. Each NaplesPU application must be linked together with two additional object files:

* ''crt0.o'', is the object file resulting of the compilation of the start routine for the custom platform, composed of operations needed to set-up the platform.
* ''vectors.o'', is the Interrupt Vector Table.

== Relocations ==
This section explains how the relocations are implemented in NaplesPU.
All relocations are specified in the ''relocateOne'' method implementation. By looking at the target ISA, LLD must check for each instruction type in which an immediate value is specified to verify if it can fit the machine instruction field.

<syntaxhighlight>
void NaplesPU::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
int64_t Offset;
switch (Type) {
default:
fatal("unrecognized reloc " + Twine(Type));
case R_NUPLUS_ABS32:
write32le(Loc, Val);
break;
case R_NUPLUS_BRANCH:
//Check Offset for J-Type Instructions
checkInt(Loc, Val, 18, Type);
applyNaplesPUReloc<18, 0>(Loc, Type, Val);
break;
case R_NUPLUS_PCREL_MEM:
//Check Offset for M-Type Instructions
checkInt(Loc, Val, 9, Type);
applyNaplesPUReloc<9, 3>(Loc, Type, Val);
break;
case R_NUPLUS_PCREL_LEA:
//Check Offset for I-Type Instructions
checkInt(Loc, Val, 9, Type);
applyNaplesPUReloc<9, 3>(Loc, Type, Val);
break;
case R_NUPLUS_ABS_HIGH_LEA:
//Check Offset for MOVEI-Type Instructions
checkInt(Loc, (Val >> 16) & 0xFFFF , 16, Type);
applyNaplesPUReloc<16, 2>(Loc, Type, (Val >> 16) & 0xFFFF);
break;
case R_NUPLUS_ABS_LOW_LEA:
//Check Offset for MOVEI-Type Instructions
checkInt(Loc, (Val) & 0xFFFF , 16, Type);
applyNaplesPUReloc<16, 2>(Loc, Type, (Val) & 0xFFFF);
break;
}
}
</syntaxhighlight>

All of these implemented relocations relies on the method ''applyNaplesPURelocation'' that simply writes back the value into the instruction.

== Linkerscript ==

All memory images generated for NaplesPU must be linked in a proper way. This way is specified by the linkerscript:

<syntaxhighlight>
stacks_dim = 16K;
stacks_base = 0x80000;
threads_per_core = 0x8;

SECTIONS
{
. = 0x00000380;
.text.vectors : {
*vectors.o(.text)
. = 0x00000400;
}

.text.start : {
*crt0.o(.text)
}
.text : { *(.text) }

. = 0x00800000;
.data : { *(.data) }

. = ALIGN(64);
scratchpad : { *(scratchpad) }

.bss : { *(.bss) }

.eh_frame : { *(.eh_frame) }

}
</syntaxhighlight>

As shown above, the linker script commonly defines where the sections must be placed into the memory. Also, it solves undefined symbols of the start routine, specifying the stack size per-thread, the number of threads and the starting address for the stack frame.

NaplesPU LLD Linker

2019-06-21T15:20:46Z

Francesco: Francesco moved page Nu+ LLD Linker to NaplesPU LLD Linker

LLD is the LLVM proprietary linker. It is based on the GNU linker, and it is compatible to it in terms of arguments accepted. It also fully supports the ''ELF'' generation but also, in a progressive lower percentage, ''PE/COFF'', ''Mach-O'', ''WebAssembly'' and custom linker-scripts.
LLD is built as a set of libraries to join the main idea of the software modular design.

The nu+ implementation of LLD is made on an ELF-based approach, by adding a new Target class inside lld/ELF/Arch folder. [[NuPlus.cpp]] contains the ''relocation'' logic and other information needed to support nu+. Each nu+ application must be linked together with two additional object files:

* ''crt0.o'', is the object file resulting of the compilation of the start routine for the custom platform, composed of operations needed to set-up the platform.
* ''vectors.o'', is the Interrupt Vector Table.

== Relocations ==
This section explains how the relocations are implemented in nu+.
All relocations are specified in the ''relocateOne'' method implementation. By looking at the target ISA, LLD must check for each instruction type in which an immediate value is specified to verify if it can fit the machine instruction field.

<syntaxhighlight>
void NuPlus::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
int64_t Offset;
switch (Type) {
default:
fatal("unrecognized reloc " + Twine(Type));
case R_NUPLUS_ABS32:
write32le(Loc, Val);
break;
case R_NUPLUS_BRANCH:
//Check Offset for J-Type Instructions
checkInt(Loc, Val, 18, Type);
applyNuPlusReloc<18, 0>(Loc, Type, Val);
break;
case R_NUPLUS_PCREL_MEM:
//Check Offset for M-Type Instructions
checkInt(Loc, Val, 9, Type);
applyNuPlusReloc<9, 3>(Loc, Type, Val);
break;
case R_NUPLUS_PCREL_LEA:
//Check Offset for I-Type Instructions
checkInt(Loc, Val, 9, Type);
applyNuPlusReloc<9, 3>(Loc, Type, Val);
break;
case R_NUPLUS_ABS_HIGH_LEA:
//Check Offset for MOVEI-Type Instructions
checkInt(Loc, (Val >> 16) & 0xFFFF , 16, Type);
applyNuPlusReloc<16, 2>(Loc, Type, (Val >> 16) & 0xFFFF);
break;
case R_NUPLUS_ABS_LOW_LEA:
//Check Offset for MOVEI-Type Instructions
checkInt(Loc, (Val) & 0xFFFF , 16, Type);
applyNuPlusReloc<16, 2>(Loc, Type, (Val) & 0xFFFF);
break;
}
}
</syntaxhighlight>

All of these implemented relocations relies on the method ''applyNuPlusRelocation'' that simply writes back the value into the instruction.

== Linkerscript ==

All memory images generated for nu+ must be linked in a proper way. This way is specified by the linkerscript:

<syntaxhighlight>
stacks_dim = 16K;
stacks_base = 0x80000;
threads_per_core = 0x8;

SECTIONS
{
. = 0x00000380;
.text.vectors : {
*vectors.o(.text)
. = 0x00000400;
}

.text.start : {
*crt0.o(.text)
}
.text : { *(.text) }

. = 0x00800000;
.data : { *(.data) }

. = ALIGN(64);
scratchpad : { *(scratchpad) }

.bss : { *(.bss) }

.eh_frame : { *(.eh_frame) }

}
</syntaxhighlight>

As shown above, the linker script commonly defines where the sections must be placed into the memory. Also, it solves undefined symbols of the start routine, specifying the stack size per-thread, the number of threads and the starting address for the stack frame.

Nu+ LLD Linker

2019-06-21T15:20:46Z

Francesco: Francesco moved page Nu+ LLD Linker to NaplesPU LLD Linker

#REDIRECT [[NaplesPU LLD Linker]]

NaplesPUMCInstLower.cpp

2019-06-21T15:05:53Z

Francesco:

The NaplesPUMCInstLower class transforms the MachineInstr object into a simplified version, the MCInst one.

<syntaxhighlight>
//===-- NaplesPUMCInstLower.cpp - Convert NaplesPU MachineInstr to MCInst -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains code to lower NaplesPU MachineInstrs to their corresponding
// MCInst records.
//
//===----------------------------------------------------------------------===//

#include "NaplesPUAsmPrinter.h"
#include "NaplesPUInstrInfo.h"
#include "NaplesPUMCInstLower.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Debug.h"

#define GET_REGINFO_ENUM
#include "NaplesPUGenRegisterInfo.inc"

using namespace llvm;

NaplesPUMCInstLower::NaplesPUMCInstLower(NaplesPUAsmPrinter &asmprinter)
: AsmPrinter(asmprinter) {}

void NaplesPUMCInstLower::Initialize(MCContext *C) {
Ctx = C;
}

//Derived from MipsMCInstLower
MCOperand NaplesPUMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
MachineOperandType MOTy,
unsigned Offset) const {
MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
const MCSymbol *Symbol;

switch (MOTy) {
case MachineOperand::MO_MachineBasicBlock:
Symbol = MO.getMBB()->getSymbol();
break;

case MachineOperand::MO_GlobalAddress:
Symbol = AsmPrinter.getSymbol(MO.getGlobal());
Offset += MO.getOffset();
break;

case MachineOperand::MO_BlockAddress:
Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
Offset += MO.getOffset();
break;

case MachineOperand::MO_ExternalSymbol:
Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
Offset += MO.getOffset();
break;
case MachineOperand::MO_JumpTableIndex:
Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
break;
case MachineOperand::MO_ConstantPoolIndex:
Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
Offset += MO.getOffset();
break;

default:
llvm_unreachable("<unknown operand type>");
}

//TODO: controllare differenze con MIPS e come mai nel case manca MO_MCSymbol (anche nella funzione successiva)
const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Symbol, Kind, *Ctx);
if (!Offset)
return MCOperand::createExpr(MCSym);

// Assume offset is never negative.
assert(Offset > 0);
const MCConstantExpr *OffsetExpr = MCConstantExpr::create(Offset, *Ctx);
const MCBinaryExpr *Add = MCBinaryExpr::createAdd(MCSym, OffsetExpr, *Ctx);
return MCOperand::createExpr(Add);
}

MCOperand NaplesPUMCInstLower::LowerOperand(const MachineOperand &MO,
unsigned offset) const {
MachineOperandType MOTy = MO.getType();

switch (MOTy) {
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) break;
return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
return MCOperand::createImm(MO.getImm() + offset);
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_BlockAddress:
return LowerSymbolOperand(MO, MOTy, offset);
case MachineOperand::MO_RegisterMask:
break;
}

return MCOperand();
}

void NaplesPUMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());

// XXX note that this chunk of code assumes a load instruction. It's also
// possible for MO_ConstantPoolIndex to appear in arithmetic. In this
// situation, the instruction would be clobbered.
//TODO: questo if usato nel caso in cui l'istruzione usa costantpool o jumptable.
// noi non abbiamo la jump table. E la costant pool?? controllare e modificare
if (MI->getNumOperands() > 1 &&
(MI->getOperand(1).getType() == MachineOperand::MO_ConstantPoolIndex ||
MI->getOperand(1).getType() == MachineOperand::MO_JumpTableIndex)) {
OutMI.addOperand(LowerOperand(MI->getOperand(0))); // result

const MachineOperand &cpEntry = MI->getOperand(1);

// This is a PC relative constant pool access. Add the PC register
// to this instruction to match what the assembly parser produces
// (and InstPrinter/Encoder expects)
// It should look like this:
// <MCInst #97 LWi <MCOperand Reg:8> <MCOperand Reg:3> <MCOperand
// Expr:(foo)>>
OutMI.addOperand(MCOperand::createReg(NaplesPU::PC_REG));
const MCSymbol *Symbol;
if (MI->getOperand(1).getType() == MachineOperand::MO_ConstantPoolIndex)
Symbol = AsmPrinter.GetCPISymbol(cpEntry.getIndex());
else
Symbol = AsmPrinter.GetJTISymbol(cpEntry.getIndex());

const MCSymbolRefExpr *MCSym =
MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, *Ctx);
MCOperand MCOp = MCOperand::createExpr(MCSym);
OutMI.addOperand(MCOp);
} else {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp = LowerOperand(MO);

if (MCOp.isValid())
OutMI.addOperand(MCOp);
}
}
}
</syntaxhighlight>

NaplesPUMCCodeEmitter.cpp

2019-06-21T15:05:33Z

Francesco:

NaplesPUMCCodeEmitter class transforms MCInst objects into binary code representation.

<syntaxhighlight>
//===-- NaplesPUMCCodeEmitter.cpp - Convert NaplesPU code to machine code -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the NaplesPUMCCodeEmitter class.
//
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/NaplesPUFixupKinds.h"
#include "MCTargetDesc/NaplesPUMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

using namespace llvm;

#define DEBUG_TYPE "mccodeemitter"

STATISTIC(MCNumEmitted, "Number of MC instructions emitted");

namespace {
class NaplesPUMCCodeEmitter : public MCCodeEmitter {
NaplesPUMCCodeEmitter(const NaplesPUMCCodeEmitter &) = delete;
void operator=(const NaplesPUMCCodeEmitter &) = delete;
MCContext &Ctx;

public:
NaplesPUMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx): Ctx(ctx) {}

// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;

unsigned encodeMemoryOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeLEAValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeABShValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeABSlValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

// Emit one byte through output stream (from MCBlazeMCCodeEmitter)
void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; }

void EmitLEConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
assert(Size <= 8 && "size too big in emit constant");

for (unsigned i = 0; i != Size; ++i) {
EmitByte(Val & 255, OS);
Val >>= 8;
}
}

};
} // end anonymous namespace

MCCodeEmitter *llvm::createNaplesPUMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new NaplesPUMCCodeEmitter(MCII, Ctx);
}

// Return binary encoding of operand.
unsigned NaplesPUMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {

if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());

if (MO.isImm())
return static_cast<unsigned>(MO.getImm());

return 0;
}

void NaplesPUMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
EmitLEConstant(Bits, 4, OS);

++MCNumEmitted; // Keep track of the # of mi's emitted.
}

unsigned NaplesPUMCCodeEmitter::encodeABShValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// with LEAH the second operand is expected to be the global address
//MCOperand address = MI.getOperand(1);
// the third operand is the label used in the asm
//MCOperand address_asm = MI.getOperand(2);

if (MI.getOperand(1).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(1).getExpr(),
MCFixupKind(NaplesPU::fixup_NaplesPU_Absh)));
} else if ( MI.getOperand(2).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(2).getExpr(),
MCFixupKind(NaplesPU::fixup_NaplesPU_Absh)));
}

return 0;
}

unsigned NaplesPUMCCodeEmitter::encodeABSlValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// with LEAH the third operand is expected to be the global address
//MCOperand address = MI.getOperand(2);
// the fourth operand is the label used in the asm
//MCOperand address_asm = MI.getOperand(3);

if (MI.getOperand(2).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(2).getExpr(),
MCFixupKind(NaplesPU::fixup_NaplesPU_Absl)));
} else if (MI.getOperand(3).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(3).getExpr(),
MCFixupKind(NaplesPU::fixup_NaplesPU_Absl)));
}

return 0;
}

unsigned NaplesPUMCCodeEmitter::encodeLEAValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
MCOperand baseReg = MI.getOperand(1);
MCOperand offsetOp = MI.getOperand(2);

assert(baseReg.isReg() && "First operand of LEA op is not register.");
unsigned encoding = Ctx.getRegisterInfo()->getEncodingValue(baseReg.getReg())<<10;
if (offsetOp.isExpr()) {
// Load with a label. This is a PC relative load. Add a fixup.
Fixups.push_back(MCFixup::create(
0, offsetOp.getExpr(),
MCFixupKind(NaplesPU::fixup_NaplesPU_PCRel_Lea)));
} else if (offsetOp.isImm())
encoding |= static_cast<short>(offsetOp.getImm())<<1;
else
assert(offsetOp.isImm() && "Second operand of LEA op is unknown type.");

return encoding;
}

// Encode NaplesPU Memory Operand. The result is a packed field with the
// register in the low 5 bits and the offset in the remainder. The instruction
// patterns will put these into the proper part of the instruction
// (NaplesPUInstrFormats.td).
unsigned
NaplesPUMCCodeEmitter::encodeMemoryOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned encoding;

MCOperand baseReg;
MCOperand offsetOp;

baseReg = MI.getOperand(1);
offsetOp = MI.getOperand(2);

// Register
// This is register/offset. No need for relocation.
assert(baseReg.isReg() && "First operand is not register.");
//encoding just the register
encoding = Ctx.getRegisterInfo()->getEncodingValue(baseReg.getReg());
// Offset
if (offsetOp.isExpr()) {
// Load with a label. This is a PC relative load. Add a fixup.
// XXX Note that this assumes unmasked instructions. A masked
// instruction will not work and should not be used. Check for this
// and return an error.
Fixups.push_back(
MCFixup::create(0, offsetOp.getExpr(),
MCFixupKind(NaplesPU::fixup_NaplesPU_PCRel_Mem)));
} else if (offsetOp.isImm())
encoding |= static_cast<short>(offsetOp.getImm()) << 6;
else
assert(offsetOp.isImm() && "Second operand of memory op is unknown type.");
return encoding;
}

// encodeBranchTargetOpValue - Return binary encoding of the jump
// target operand. If the machine operand requires relocation,
// record the relocation and return zero.
unsigned NaplesPUMCCodeEmitter::encodeBranchTargetOpValue(
const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {

const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isImm())
return MO.getImm();

assert(MO.isExpr() &&
"encodeBranchTargetOpValue expects only expressions or an immediate");

const MCExpr *Expr = MO.getExpr();
Fixups.push_back(
MCFixup::create(0, Expr, MCFixupKind(NaplesPU::fixup_NaplesPU_Branch)));
return 0;
}

#include "NaplesPUGenMCCodeEmitter.inc"

</syntaxhighlight>

NaplesPUInstPrinter.cpp

2019-06-21T15:05:13Z

Francesco:

NaplesPUInstPrinter contains method to print assembly instructions from MCInst objects.
<syntaxhighlight>
//===-- NaplesPUInstPrinter.cpp - Convert NaplesPU MCInst to assembly syntax -----==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an NaplesPU MCInst to a .s file.
//
//===----------------------------------------------------------------------===//

#include "NaplesPUInstPrinter.h"
#include "MCTargetDesc/NaplesPUMCTargetDesc.h"
#include "NaplesPUInstrInfo.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;

#define DEBUG_TYPE "asm-printer"

using namespace llvm;

#include "NaplesPUGenAsmWriter.inc"

namespace
{
void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI,
raw_ostream &OS)
{
int Offset = 0;
const MCSymbolRefExpr *SRE;

if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr))
{
SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS());
assert(SRE && CE && "Binary expression must be sym+const.");
Offset = CE->getValue();
}
else if (!(SRE = dyn_cast<MCSymbolRefExpr>(Expr)))
{
Expr->print(OS, MAI);
return;
}

MCSymbolRefExpr::VariantKind Kind = SRE->getKind();

OS << SRE->getSymbol();

if (Offset)
{
if (Offset > 0)
OS << '+';
OS << Offset;
}

if (Kind != MCSymbolRefExpr::VK_None)
OS << ')';
}
}

void NaplesPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
{
// TODO: (Catello) magic errs()
//errs()<< "";
OS << StringRef(getRegisterName(RegNo)).lower();
}

void NaplesPUInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI)
{
// NOP is or s0, s0, 0
if (MI->getOpcode() == NaplesPU::ORSSI && MI->getOperand(0).isReg() &&
MI->getOperand(0).getReg() == NaplesPU::S0 && MI->getOperand(1).isReg() &&
MI->getOperand(1).getReg() == NaplesPU::S0 && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0)
{
O << "\tnop";
return;
}

printInstruction(MI, O);
printAnnotation(O, Annot);
}

void NaplesPUInstPrinter::printOperand(const MCInst *MI, int opNum,
raw_ostream &O)
{
const MCOperand &MO = MI->getOperand(opNum);

if (MO.isReg())
{
printRegName(O, MO.getReg());
return;
}

if (MO.isImm())
{
O << (int)MO.getImm();
return;
}

assert(MO.isExpr() && "Unknown operand kind in printOperand");
if (MO.isExpr())
{
printExpr(MO.getExpr(), &MAI, O);
}
return;
}

void NaplesPUInstPrinter::printMemOperand(const MCInst *MI, int opNum,
raw_ostream &O)
{
if (MI->getOperand(opNum).isExpr())
{
// Abs instructions
printOperand(MI, opNum, O);
}
else if (MI->getOperand(opNum + 1).isExpr())
{
// PC relative memory access to a local label
printOperand(MI, opNum + 1, O);
}
else
{
// Register/offset
assert(MI->getOperand(opNum).isReg());
assert(MI->getOperand(opNum + 1).isImm());

if (MI->getOperand(opNum + 1).getImm())
printOperand(MI, opNum + 1, O);

O << "(";
printOperand(MI, opNum, O);
O << ")";
}
}

</syntaxhighlight>

NaplesPUInstPrinter.cpp

2019-06-21T15:04:59Z

Francesco:

NuPlusInstPrinter contains method to print assembly instructions from MCInst objects.
<syntaxhighlight>
//===-- NuPlusInstPrinter.cpp - Convert NuPlus MCInst to assembly syntax -----==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an NuPlus MCInst to a .s file.
//
//===----------------------------------------------------------------------===//

#include "NuPlusInstPrinter.h"
#include "MCTargetDesc/NuPlusMCTargetDesc.h"
#include "NuPlusInstrInfo.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;

#define DEBUG_TYPE "asm-printer"

using namespace llvm;

#include "NuPlusGenAsmWriter.inc"

namespace
{
void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI,
raw_ostream &OS)
{
int Offset = 0;
const MCSymbolRefExpr *SRE;

if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr))
{
SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS());
assert(SRE && CE && "Binary expression must be sym+const.");
Offset = CE->getValue();
}
else if (!(SRE = dyn_cast<MCSymbolRefExpr>(Expr)))
{
Expr->print(OS, MAI);
return;
}

MCSymbolRefExpr::VariantKind Kind = SRE->getKind();

OS << SRE->getSymbol();

if (Offset)
{
if (Offset > 0)
OS << '+';
OS << Offset;
}

if (Kind != MCSymbolRefExpr::VK_None)
OS << ')';
}
}

void NuPlusInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
{
// TODO: (Catello) magic errs()
//errs()<< "";
OS << StringRef(getRegisterName(RegNo)).lower();
}

void NuPlusInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI)
{
// NOP is or s0, s0, 0
if (MI->getOpcode() == NuPlus::ORSSI && MI->getOperand(0).isReg() &&
MI->getOperand(0).getReg() == NuPlus::S0 && MI->getOperand(1).isReg() &&
MI->getOperand(1).getReg() == NuPlus::S0 && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0)
{
O << "\tnop";
return;
}

printInstruction(MI, O);
printAnnotation(O, Annot);
}

void NuPlusInstPrinter::printOperand(const MCInst *MI, int opNum,
raw_ostream &O)
{
const MCOperand &MO = MI->getOperand(opNum);

if (MO.isReg())
{
printRegName(O, MO.getReg());
return;
}

if (MO.isImm())
{
O << (int)MO.getImm();
return;
}

assert(MO.isExpr() && "Unknown operand kind in printOperand");
if (MO.isExpr())
{
printExpr(MO.getExpr(), &MAI, O);
}
return;
}

void NuPlusInstPrinter::printMemOperand(const MCInst *MI, int opNum,
raw_ostream &O)
{
if (MI->getOperand(opNum).isExpr())
{
// Abs instructions
printOperand(MI, opNum, O);
}
else if (MI->getOperand(opNum + 1).isExpr())
{
// PC relative memory access to a local label
printOperand(MI, opNum + 1, O);
}
else
{
// Register/offset
assert(MI->getOperand(opNum).isReg());
assert(MI->getOperand(opNum + 1).isImm());

if (MI->getOperand(opNum + 1).getImm())
printOperand(MI, opNum + 1, O);

O << "(";
printOperand(MI, opNum, O);
O << ")";
}
}

</syntaxhighlight>

NaplesPUInstPrinter.cpp

2019-06-21T15:04:55Z

Francesco:

NaplesPUISelLowering.cpp

2019-06-21T15:04:14Z

Francesco:

=NaplesPUTargetLowering class=
[[Category:C++ Classes]]
The '''NaplesPUTargetLowering''' class implements the [http://llvm.org/docs/CodeGenerator.html#the-targetlowering-class TargetLowering] interface and is contained in the NaplesPUISelLowering.h/.cpp files.
The class must describe how to lower LLVM code to machine code. This has two main components:
#Which ValueTypes are natively supported by the target.
#Which operations are supported for supported ValueTypes.

The '''NaplesPUTargetLowering''' class can be thought of being composed by four sections:
#The class constructor.
#The custom [https://llvm.org/docs/CodeGenerator.html#introduction-to-selectiondags SDNode] lowering.
#The custom [http://llvm.org/docs/CodeGenerator.html#machineinstr MachineInstruction] insertion.
#The implementation of other TargetLowering virtual methods.

== The Class Constructor ==
The NaplesPUTargetLowering class constructor describes the MachineValueTypes supported by NaplesPU with the corresponding [[NaplesPURegisterInfo.td |RegisterClass]], the operations not supported for supported MachineValueTypes and the corresponding action to perform, other useful information concerning the Instruction-Lowering phase.
These informations are described using the ''protected'' methods provided by the base class ''TargetLowering''.

=== addRegisterClass ===
The '''addRegisterClass''' method tells the Code Generator the supported MachineValueTypes and the RegisterClass to use. The '''MachineValueTypes''' are defined in the '''MVT''' class in "compiler/include/llvm/CodeGen/MachineValueType.h", while the RegisterClass are those defined in [[NaplesPURegisterInfo.td]]. The following table summarize the supported MachineValueTypes and the relative RegisterClass.

{| class="wikitable"
! style="font-weight: bold;" | RegisterClass
! style="font-weight: bold;" | MVT
|-
| GPR32RegClass
| i32, f32
|-
| GPR64RegClass
| i64, f64
|-
| VR512WRegClass
| v16i32, v16f32
|-
| VR512LRegClass
| v8i64, v8f64
|}

The corresponding code is:

<syntaxhighlight lang="c++" line='line'>
// Scalar data types
addRegisterClass(MVT::i32, &NaplesPU::GPR32RegClass);
addRegisterClass(MVT::f32, &NaplesPU::GPR32RegClass);

addRegisterClass(MVT::i64, &NaplesPU::GPR64RegClass);
addRegisterClass(MVT::f64, &NaplesPU::GPR64RegClass);

// Vector data types (512-bit wide)
addRegisterClass(MVT::v16i32, &NaplesPU::VR512WRegClass);
addRegisterClass(MVT::v16f32, &NaplesPU::VR512WRegClass);

addRegisterClass(MVT::v8i64, &NaplesPU::VR512LRegClass);
addRegisterClass(MVT::v8f64, &NaplesPU::VR512LRegClass);
</syntaxhighlight>

=== setOperationAction ===
The '''setOperationAction''' method is used to tell the Code Generator the unsupported operation for the specified MachineValueType and the action to perform, this because by default every operation is considered '''Legal'''.

This information is used by the LLVM Code Generator during the [http://llvm.org/docs/CodeGenerator.html#instruction-selection-section InstructionSelection] phase. So the input to give the function are the '''Operation Code''' (defined in the '''NodeType''' enum in "/compiler/include/llvm/CodeGen/ISDOpcodes.h"), the associated '''MachineValueTypes''' and the '''action''' to perform in order to legalize the operation. At this stage each operation is described by a Node in the SelectionDAG.

The action must be one of those in the '''LegalizeAction''' enum contained in the '''TargetLoweringBase''' class (/compiler/include/llvm/Target/TargetLowering.h). Hence the possible actions are:
* '''Legal''', the target natively supports this operation.
* '''Promote''', this operation should be executed in a larger type.
* '''Expand''', try to expand this to other ops, otherwise use a libcall.
* '''LibCall''', don't try to expand this to other ops, always use a libcall.
* '''Custom''', use the '''LowerOperation''' hook to implement custom lowering.

The most used in the NaplesPU+ backend are the ''Expand'' and the ''Custom'' actions.
As mentioned before, the '''Expand''' action tries to expand the node using equivalent operations, if this cannot be done, a function call is generated. The signature is defined in the '''InitLibcallNames''' in "/compiler/lib/CodeGen/TargetLoweringBase.cpp".
With the '''Custom''' action, the lowering must be manually done implementing a proper function.

== Custom Lowering ==

When an operation must be custom lowered (using setOperationAction with Custom action), LLVM calls the '''LowerOperation''' function passing it the Node to lower and the DAG. The lowering is handled in this way:
*The '''LowerOperation''' function is implemented with a switch on the Node Opcode, according to its value returns the SDValue of a specific function.
*The operand specific functions are named as ''LowerOPERAND_NAME'' and they must generate the Machine Nodes that correspond to the input Node (object of SDValue class).

=== Selection DAG Node representation ===
LLVM uses mainly three classes to represent a SelectionDAG: '''SDNode''' and '''SDValue''' and '''SDUse'''. They are defined in "/compiler/include/llvm/CodeGen/SelectionDAGNodes.h".

The '''SDNode''' class is the representation of a ''node'' in the Selection DAG and stores information about the operation type and its operands (list of SDUse objects).
The '''SDValue''' represents the output value of a SDNode. However, a SDNode may return muiltiple valuesas the result of a computation. Thus the SDValue stores informations about the SDNode as well as which return value to use from that node.
The '''SDUse''' class represents a a use of a SDNode and holds an SDValue, which records the SDNode being used and the result number, a pointer to the SDNode using the value, and Next and Prev pointers, which link together all the uses of an SDNode.

From a visual point of view, we can imagine a Selection DAG as composed by nodes and and edges.
A node has an operand list, an operation, an ID (all of them stored in a SDNode object) and one or more output values (each one represented by a SDValue object).
An arrow goes from an input operand to a return value (informations stored in a a SDUse object) and represents data flow among nodes. There are also "chain" edges that represent control flow and provide an ordering between nodes that have side effects such as loads, stores, calls, returns, etc.

It is possible to visualize, during a compilation, the DAGs LLVM generates by passing the flag "-mllvm -debug=isel" (textual form) or using the "-view*" options (visual form). Note that LLVM must be compiled in "Debug" mode in order to show such informations.

=== Lowering ===
The purpose of a custom lowering node function is to substitute the input node with a '''legal''' node or DAG that performs the same operation. The difference among a "legal" DAG and an "illegal" one, is that the legal DAG uses only operations an types supported by the machine.

For example lets analyze "LowerFNEG" function. It is used to lower the FNEG node using legal nodes.
The FNEG operation must perform the negation of a floating-point value (see "/compiler/include/llvm/CodeGen/ISDOpcodes.h" for definition). Since the NaplesPU architecture does not have an instruction to directly perform the operation, we have to perform the lowering manually.

The first step is to declare in the NaplesPUTargetLowering class constructor that the FNEG operation must be custom lowered for all the supported floating-point types.

<syntaxhighlight lang="c++" line='line'>
// Note that this is just an example code. In NaplesPU backed
// we use for loops to make the file more readable.
setOperationAction(ISD::FNEG, MVT::f32, Custom);
setOperationAction(ISD::FNEG, MVT::f64, Custom);
setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
</syntaxhighlight>

Then we update the switch in the "LowerOperation" function so that calls the "LowerFNEG" function, previously defined in the NaplesPUTargetLowering" interface (located in "/compiler/lib/Target/NaplesPU/NaplesPUISelLowering.h").

<syntaxhighlight lang="c++" line='line'>
SDValue NaplesPUTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
...
case ISD::FNEG:
return LowerFNEG(Op, DAG);
...
}
</syntaxhighlight>

<syntaxhighlight lang="c++" line='line'>
class NaplesPUTargetLowering : public TargetLowering {
public:
...
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
...
}
</syntaxhighlight>

Then we define the "LowerFNEG" function.

<syntaxhighlight lang="c++" line='line'>
SDValue NaplesPUTargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT ResultVT = Op.getValueType().getSimpleVT();
MVT IntermediateVT;

if (ResultVT.isVector()) {
IntermediateVT =
(ResultVT.getVectorElementType() == MVT::f32) ? MVT::v16i32 : MVT::v8i64;
} else {
IntermediateVT =
(ResultVT.getScalarType() == MVT::f32) ? MVT::i32 : MVT::i64;
}

SDValue rhs = (IntermediateVT.getScalarType() == MVT::i32) ?
DAG.getConstant(0x80000000, DL, MVT::i32) :
DAG.getConstant(0x8000000000000000, DL, MVT::i64);

SDValue iconv;
if (ResultVT.isVector())
rhs = DAG.getNode(NaplesPUISD::SPLAT, DL, IntermediateVT, rhs);

iconv = DAG.getNode(ISD::BITCAST, DL, IntermediateVT, Op.getOperand(0));
SDValue flipped = DAG.getNode(ISD::XOR, DL, IntermediateVT, iconv, rhs);
return DAG.getNode(ISD::BITCAST, DL, ResultVT, flipped);
}

</syntaxhighlight>

The two inputs are "SDValue Op" and "SelectionDAG &DAG". '''Op''' is the node that must be lowered, in this case an FNEG operation. It is a SDValue object because in this way we have also information about the output value. '''DAG''' is used to create the nodes containing the operations the one contained in '''Op'''.

[[File:FNEGScalar.png|frame|This image shows how the FNEG is lowered in case of scalar floating-point value.]]
[[File:FNEGVector.png|frame|This image shows how the FNEG is lowered in case of vector floating-point value. Differently from the scalar case, the SPLAT node is added before the XOR.]]

The function must return the last of the legal nodes generated. The figures belove show lowering of FNEG node.

According to the IEEE 754 standard the MSB is the sign bit, thus to negate a floating-point value the MSB must be inverted. This could be done by XORing the floating-point value with 0x80000000 (for 32-bit floating-point) or 0x8000000000000000 (for 64-bit floating-point).
The XOR operation, however, can only be done between integer operations. Thus floating-point operand must be bitcasted into an integer before XORing it. The bitcast operation tells LLVM to interpret a value with a different type with same width (e.g. i32 <-> f32). The inverse bistacst operation need to be done also for the XOR return value that must be interpreted as a floating-point.

In case of the FNEG is done on a vector type, we must add another node to correctly load the constant 0x80000000 (or 0x8000000000000000). This is done through the SPLAT operation. This operation takes a scalar and copies it on all the vector elements. In hardware it corresponds to a move operation.

The function code first checks the result type, in order to determine the appropriate integer type for the constant and XOR operation (It is stored in the "IntermediateVT" variable).
Then we use the "getConstant" method to generate the Constant Node. The method takes the constant value, a SDLoc object containing the '''Op''' IR location info and the value type.

If the input operand type is a vector, we generate a SPLAT node.
Then we create the XOR node preceded and succeeded by the SPLAT operations.

The method "getNode" is used to generate nodes. It takes the node Opcode, the SDLoc object, the output value type and the input operands. The function returns only the SDValue of the last BITCAST operation since it stores the informations about the previous nodes.

The SPLAT node does not belong to the "ISD" namespace but to the "NaplesPUISD" namespace. This because LLVM does not have this node type and is defined only in the NaplesPU back-end. It will be resolved later during the Select phase using one of the patterns defined in [[NaplesPUInstrInfo.td]].

The other lowering functions act in a similar way. They lower the input node using the SelectionDAG class methods according to the operation to implement and the input node informations.
However, there are cases in which nodes tagged to be custom lowered are simply expanded. This is done, for example, in the "LowerBUILD_VECTOR" function in which the BUILD_VECTOR node must be lowered with a SPLAT operation only if the vector it tries to build is composed by the same scalar value, otherwise the expansion of the BUILD_VECTOR node is sufficient.

The way to tell the Code Generator that the node must be expanded is to return an empty SDValue.

<syntaxhighlight lang="c++" line='line'>
SDValue NaplesPUTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
// MVT VT = Op.getValueType().getSimpleVT();
SDLoc DL(Op);

if (isSplatVector(Op.getNode())) {
// This is a constant node that is duplicated to all lanes.
// Convert it to a SPLAT node.
return CheckSplat(Op, Op.getOperand(0), DAG);
}

return SDValue(); // Expand
}

</syntaxhighlight>

== Custom MachineInstruction Insertion ==

Another way to lower unsupported operations is to manually emit Machine Instructions. The emission of Machine Instructions takes place just before the '''Register Allocation'''. It is important to remember that the Machine Instructions are still in SSA form, so care must be taken when creating virtual registers.

To instruct LLVM about what operations must have a custom inserter, a (pseudo)instruction in [[NaplesPUInstrInfo.td]] with the '''usesCustomInserter''' flag setted to 1 must be defined.

When an MachineInstruction must be custom inserted, LLVM calls the '''EmitInstrWithCustomInserter''' function passing it the Machine Instruction to lower and the Basic Block, the instruction belongs:
*The '''EmitInstrWithCustomInserter''' function is implemented with a switch on the Machine Instruction Opcode, according to its value returns the modified input basic block.
*The operand specific functions are named as ''EmitOPERATION_NAME'' and they must generate the instructions that correspond to the input Machine Instruction.

=== Instruction Insertion ===
The purpose of a custom instruction inserter function is to substitute the input Machine Instruction with instructions that perform the same operation.

For example, lets consider the "EmitLoadI32" function.

In NaplesPU, the immediate field of type I instruction is 16 bits wide so to load a 32-bit immediate value the instruction couple MOVEIH-MOVEIL must be emitted.

The EmitLoadI32 function is called by the EmitInstrWithCustomInserter hook function. The latter is called when the Code Generator encounters a machine instruction which has the usesCustomInserter flag setted to 1.

Therefore, in NaplesPUInstrInfo.td, the pseudo-instruction '''LoadI32''' is defined with usesCustomInserter = 1. The corresponding node is generated during the Select phase, when the pattern "(set i32:$dst, (i32 imm:$val))" is detected.

<syntaxhighlight lang="c++" line='line'>
let usesCustomInserter = 1 in {
def LoadI32 : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$val),
[(set i32:$dst, (i32 imm:$val))]>;

...

}
</syntaxhighlight>

When must emit the instruction corresponding to '''LoadI32''', the "EmitLoadI32" is called (through the EmitInstrWithCustomInserter hook function).
The emit functions have at least two inputs ([http://llvm.org/docs/CodeGenerator.html#the-machineinstr-class MachineInstr] *MI and [http://llvm.org/docs/CodeGenerator.html#the-machinebasicblock-class MachineBasicBlock] *BB) and must return the MachineBasicBlock modified.

To emit instructions the '''BuildMI''' interface (defined in "/compiler/include/llvm/CodeGen/MachineInstrBuilder.h") is used. This interface allows a simple way to generate instructions, providing methods like addReg, addImm and etc.

In the case of the EmitLoadI32, first the immediate values is taken from the LoadI32 operation, then the InsertLoad32Immediate function is called. This function is responsible of generating the MOVEIH-MOVEIL instruction couple. At last LoadI32 is deleted and the resulting Basic Block is returned.

<syntaxhighlight lang="c++" line='line'>
MachineBasicBlock *
NaplesPUTargetLowering::EmitLoadI32(MachineInstr *MI,
MachineBasicBlock *BB) const {

DebugLoc DL = MI->getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();

// Get the integer immediate value.
int64_t ImmOp = MI->getOperand(1).getImm();
// Call the fuction that generates the MIs.
InsertLoad32Immediate(MI, BB, TII, &DL, MI->getOperand(0).getReg(), ImmOp);

MI->eraseFromParent();

return BB;
}
</syntaxhighlight>

The InsertLoad32Immediate function uses the BuildMI interface to generate the instructions. There are several versions of BuildMI, the one used takes as inputs the MachineBasicBlock where to insert the instructions, the pointer to the MachineInstruction before which insert the new instruction, a DebugLoc and the instruction description (MCInstrDesc class object) it must generate.
The instruction description is obtained through the TargetInstrInfo get method passing it the instruction name.

Note: in a Machine Instruction the first operand is the output.

<syntaxhighlight lang="c++" line='line'>
void InsertLoad32Immediate (MachineInstr *MI, MachineBasicBlock *BB,
const TargetInstrInfo *TII, DebugLoc *DL,
unsigned DestReg, int64_t Immediate) {

BuildMI(*BB, *MI, *DL, TII->get(NaplesPU::MOVEIHSI))
.addReg(DestReg, RegState::Define)
.addImm(((Immediate >> 16) & 0xFFFF));
BuildMI(*BB, *MI, *DL, TII->get(NaplesPU::MOVEILSI))
.addReg(DestReg)
.addImm((Immediate & 0xFFFF));

}
</syntaxhighlight>

Since the instruction are still in SSA form, the code above shows a workaround to use the same destination register.

== Other Methods ==

The NaplesPUTargetLowering class redefines also some other methods used to instruct the Code Generator about the specific capabilities supported or unsupported by the NaplesPU architecture.

NaplesPUInstrInfo.td

2019-06-21T15:02:34Z

Francesco:

[[Category:Tablegen Files]]
NaplesPUInstrInfo.td and [[NaplesPUInstrFormats.td]] describe the NaplesPU instructions and the patterns to transform LLVM IR into machine code. The NaplesPUInstrInfo.td contains the instructions definition and the patterns necessary for the translation from the LLVM IR to the NaplesPU machine code.

<syntaxhighlight>
//===-- NaplesPUInstrInfo.td - Target Description for NaplesPU Target -----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the NaplesPU instructions in TableGen format.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//

include "NaplesPUInstrFormats.td"

//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Arithmetic Instructions (Format R & I)
//===----------------------------------------------------------------------===//

//Arithmetic Integer Two operands
defm OR : FArithInt_TwoOp<"or", or, 1>;
defm AND : FArithInt_TwoOp<"and", and, 2>;
defm XOR : FArithInt_TwoOp<"xor", xor, 3>;
defm ADD : FArithInt_TwoOp<"add", add, 4>;
defm SUB : FArithInt_TwoOp<"sub", sub, 5>;
defm MULL : FArithInt_TwoOp<"mull", mul, 6>;
defm MULH : FArithInt_TwoOp<"mulhs", mulhs, 7>;
defm MULHU : FArithInt_TwoOp<"mulhu", mulhu, 8>;
defm SRA : FSRInt_TwoOp<"ashr", sra, 9>;
defm SRL : FSRInt_TwoOp<"shr", srl, 10>;
defm SLL : FSRInt_TwoOp<"shl", shl, 11>;
//Arithmetic Integer One operand
defm CLZ : FArithInt_OneOp<"clz", ctlz, 12>;
defm CTZ : FArithInt_OneOp<"ctz", cttz, 13>;
//Compare Integer
defm SEQSI : FCompInt<"cmpeq", SETEQ, 14, int_npu_mask_cmpi32_eq>;//, int_npu_mask_cmpi64_eq>;
defm SNESI : FCompInt<"cmpne", SETNE, 15, int_npu_mask_cmpi32_ne>;//, int_npu_mask_cmpi64_ne>;
defm SGTSI : FCompInt<"cmpgt", SETGT, 16, int_npu_mask_cmpi32_sgt>;//, int_npu_mask_cmpi64_sgt>;
defm SGESI : FCompInt<"cmpge", SETGE, 17, int_npu_mask_cmpi32_sge>;//, int_npu_mask_cmpi64_sge>;
defm SLTSI : FCompInt<"cmplt", SETLT, 18, int_npu_mask_cmpi32_slt>;//, int_npu_mask_cmpi64_slt>;
defm SLESI : FCompInt<"cmple", SETLE, 19, int_npu_mask_cmpi32_sle>;//, int_npu_mask_cmpi64_sle>;
//Compare Unsigned
defm SGTUI : FCompInt<"cmpugt", SETUGT, 20, int_npu_mask_cmpi32_ugt>;//, int_npu_mask_cmpi64_ugt>;
defm SGEUI : FCompInt<"cmpuge", SETUGE, 21, int_npu_mask_cmpi32_uge>;//, int_npu_mask_cmpi64_uge>;
defm SLTUI : FCompInt<"cmpult", SETULT, 22, int_npu_mask_cmpi32_ult>;//, int_npu_mask_cmpi64_ult>;
defm SLEUI : FCompInt<"cmpule", SETULE, 23, int_npu_mask_cmpi32_ule>;//, int_npu_mask_cmpi64_ule>;

//Cross Product Instruction
def CROSSPROD_32 : FR_TwoOp_Unmasked_32 <
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
"crp $dst, $src0, $src1",
[(set v16i32:$dst, (int_npu_crossprodv16i32 v16i32:$src0, v16i32:$src1))],
63,
Fmt_V,
Fmt_V,
Fmt_V>;

//Shuffle
def SHUFFLEI_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
"shuffle_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (int_npu_shufflei32 v16i32:$src0, v16i32:$src1))],
24,
Fmt_V,
Fmt_V,
Fmt_V>;

//Get lane
def GET_LANEI_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, GPR32:$src1),
"getlane_i32 $dst, $src0, $src1",
[(set i32:$dst, (extractelt v16i32:$src0, i32:$src1))],
25,
Fmt_S,
Fmt_V,
Fmt_S>;

def GET_LANEIimm : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
"getlanei $dst, $src, $imm",
[(set i32:$dst, (extractelt v16i32:$src, simm9:$imm))],
25,
Fmt_S,
Fmt_V>;

//Move register - register
def MOVE_SS_32 : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
"move_i32 $dst, $src0",
[],
32,
Fmt_S,
Fmt_S>;

def MOVE_VS_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins GPR32:$src0),
"move_i32 $dst, $src0",
[(set v16i32:$dst, (splat i32:$src0))],
32,
Fmt_V,
Fmt_S>;

def MOVE_VV_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
"move_i32 $dst, $src0",
[],
32,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue", isAsmParserOnly=1 in {

def MOVE_VS_M_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins GPR32:$src0, VR512W:$oldvalue),
"move_i32 $dst, $src0",
[(set v16i32:$dst, (int_npu_vector_mixi32 (splat i32:$src0), v16i32:$oldvalue))],
32,
Fmt_V,
Fmt_S>;

def MOVE_VV_M_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
"move_i32 $dst, $src0",
[(set v16i32:$dst, (int_npu_vector_mixi32 v16i32:$src0, v16i32:$oldvalue))],
32,
Fmt_V,
Fmt_V>;

}

//Arithmetic Float Two operands
defm ADDF : FArithFloat_TwoOp<"fadd", fadd, 33>;
defm SUBF : FArithFloat_TwoOp<"fsub", fsub, 34>;
defm MULF : FArithFloat_TwoOp<"fmul", fmul, 35>;
defm DIVF : FArithFloat_TwoOp<"fdiv", fdiv, 36>;
//Compare Float
def FloatCompareType: SDTypeProfile<1, 2, [
SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>
]>;
def FGT: SDNode<"NaplesPUISD::FGT", FloatCompareType>;
def FGE: SDNode<"NaplesPUISD::FGE", FloatCompareType>;
def FLT: SDNode<"NaplesPUISD::FLT", FloatCompareType>;
def FLE: SDNode<"NaplesPUISD::FLE", FloatCompareType>;
def FEQ: SDNode<"NaplesPUISD::FEQ", FloatCompareType>;
def FNE: SDNode<"NaplesPUISD::FNE", FloatCompareType>;

defm SEQFO : FCompFloat<"cmpfeq", FEQ, 37, int_npu_mask_cmpf32_eq>;//, int_npu_mask_cmpf64_eq>;
defm SNEFO : FCompFloat<"cmpfne", FNE, 38, int_npu_mask_cmpf32_ne>;//, int_npu_mask_cmpf64_ne>;
defm SGTFO : FCompFloat<"cmpfgt", FGT, 39, int_npu_mask_cmpf32_gt>;//, int_npu_mask_cmpf64_gt>;
defm SGEFO : FCompFloat<"cmpfge", FGE, 40, int_npu_mask_cmpf32_ge>;//, int_npu_mask_cmpf64_ge>;
defm SLTFO : FCompFloat<"cmpflt", FLT, 41, int_npu_mask_cmpf32_lt>;//, int_npu_mask_cmpf64_lt>;
defm SLEFO : FCompFloat<"cmpfle", FLE, 42, int_npu_mask_cmpf32_le>;//, int_npu_mask_cmpf64_le>;

//sign extension
defm SEXT8_32 : FSext_32<"sext8", i8, 43, v16i8>;
defm SEXT16_32 : FSext_32<"sext16", i16, 44, v16i16>;

//Integer to Float conversion
def I32TOF32_SS : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
"itof_i32 $dst, $src0",
[(set f32:$dst, (sint_to_fp i32:$src0))],
48,
Fmt_S,
Fmt_S>;

def I32TOF32_VV_U : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
"itof_i32 $dst, $src0",
[(set v16f32:$dst, (sint_to_fp v16i32:$src0))],
48,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
def I32TOF32_VV_M : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
"itof_i32.m $dst, $src0",
[(set v16f32:$dst, (int_npu_vector_mixf32 (sint_to_fp v16i32:$src0), v16f32:$oldvalue))],
48,
Fmt_V,
Fmt_V>;

}

//Float to Integer conversion
def F32TOI32_SS : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
"ftoi_i32 $dst, $src0",
[(set i32:$dst, (fp_to_sint f32:$src0))],
49,
Fmt_S,
Fmt_S>;

def F32TOI32_VV_U : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
"ftoi_i32 $dst, $src0",
[(set v16i32:$dst, (fp_to_sint v16f32:$src0))],
49,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
def F32TOI32_VV_M : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
"ftoi_i32.m $dst, $src0",
[(set v16i32:$dst, (int_npu_vector_mixi32 (fp_to_sint v16f32:$src0), v16i32:$oldvalue))],
49,
Fmt_V,
Fmt_V>;

}

//===----------------------------------------------------------------------===//
// MOVEI Instructions (Format MOVEI)
//===----------------------------------------------------------------------===//

defm MOVEIL : FMOVEI_ALL<"moveil", 0>;
defm MOVEIH : FMOVEI_ALL<"moveih", 1>;
defm MOVEI : FMOVEI_ALL<"movei", 2>;

//===----------------------------------------------------------------------===//
// LOAD/STORE SPECIAL REGISTERS
//===----------------------------------------------------------------------===//

def READMR : READ_SPR<MaskReg, "read_mr", int_npu_read_mask_reg>;
def WRITEMR : WRITE_SPR<MaskReg, "write_mr", int_npu_write_mask_reg>;

//Create Mask Instruction
def CREATEMASK_32 : FR_OneOp_Unmasked_32 <
(outs GPR32:$dst),
(ins VR512W:$src0),
"crt_mask_i32 $dst, $src0",
[(set i32:$dst, (int_npu_createmaskv16i32 v16i32:$src0))],
50,
Fmt_S,
Fmt_V>;

//===----------------------------------------------------------------------===//
// MEM Instructions (Format M)
//===----------------------------------------------------------------------===//

// Scalar load to 32-bit registers
defm L32BS : FMLoadScalar_32<"_s8", sextloadi8_mem, sextloadi8_scratch, 0>;
defm L32SS : FMLoadScalar_32<"_s16", sextloadi16_mem, sextloadi16_scratch, 1>;
defm L32W : FMLoadScalar_32<"", MemLoad, ScratchpadLoad, 2>;
defm L32BU : FMLoadScalar_32<"_u8", zextloadi8_mem, zextloadi8_scratch, 4>;
defm L32SU : FMLoadScalar_32<"_u16", zextloadi16_mem, zextloadi16_scratch, 5>;
defm S32B : FMStoreScalar_32<"_8", truncstorei8_mem, truncstorei8_scratch, 32>;
defm S32S : FMStoreScalar_32<"_16", truncstorei16_mem, truncstorei16_scratch, 33>;
defm S32W : FMStoreScalar_32<"", MemStore, ScratchpadStore, 34>;
//--------------------------------------------------------------------------------//
//Vector load block
//--------------------------------------------------------------------------------//

// Vector load to 32-bit registers
defm LV32B : FMLoadVector_32<"_v16i8", sextloadv16i8_mem, sextloadv16i8_scratch,
int_npu_block_loadv16i8_masked, int_npu_block_loadv16i8_scratchpad_masked,
7>;
defm LV32S : FMLoadVector_32<"_v16i16", sextloadv16i16_mem, sextloadv16i16_scratch,
int_npu_block_loadv16i16_masked, int_npu_block_loadv16i16_scratchpad_masked,
8>;
defm LV32W : FMLoadVector_32<"_v16i32", MemLoad, ScratchpadLoad,
int_npu_block_loadv16i32_masked, int_npu_block_loadv16i32_scratchpad_masked,
9>;

defm LV32BU : FMLoadVector_32<"_v16u8", zextloadv16i8_mem, zextloadv16i8_scratch,
int_npu_block_loadv16u8_masked, int_npu_block_loadv16u8_scratchpad_masked,
11>;
defm LV32SU : FMLoadVector_32<"_v16u16", zextloadv16i16_mem, zextloadv16i16_scratch,
int_npu_block_loadv16u16_masked, int_npu_block_loadv16u16_scratchpad_masked,
12>;
//--------------------------------------------------------------------------------//
//Vector load gather
//--------------------------------------------------------------------------------//

// Vector gather to 32-bit registers
defm GLV32W : FMGather_32<"32", int_npu_gather_loadi32_scratchpad,
int_npu_gather_loadi32_scratchpad_masked,
16>;

//--------------------------------------------------------------------------------//
//Vector store block
//--------------------------------------------------------------------------------//

// Vector store from 32-bit registers
defm SV32B : FMStoreVector_32<"_v16i8", truncstorev16i8_mem, truncstorev16i8_scratch,
int_npu_block_storev16i8_masked, int_npu_block_storev16i8_scratchpad_masked,
36>;
defm SV32S : FMStoreVector_32<"_v16i16", truncstorev16i16_mem, truncstorev16i16_scratch,
int_npu_block_storev16i16_masked, int_npu_block_storev16i16_scratchpad_masked,
37>;
defm SV32W : FMStoreVector_32<"_v16i32", MemStore, ScratchpadStore,
int_npu_block_storev16i32_masked, int_npu_block_storev16i32_scratchpad_masked,
38>;

//--------------------------------------------------------------------------------//
//Vector store scatter
//--------------------------------------------------------------------------------//

// Vector scatter from 32-bit registers
defm SSV32W : FMScatter_32<"32",int_npu_scatter_storei32_scratchpad,
int_npu_scatter_storei32_scratchpad_masked,
42>;

//===----------------------------------------------------------------------===//
// Jump and Branch Instructions (Format J/JR)
//===----------------------------------------------------------------------===//

let isTerminator = 1 in {
//Unconditional jump with offset, PC:=PC+addr
def JMP : FJ<
(outs),
(ins brtarget:$addr),
"jmp $addr",
[(br bb:$addr)],
0>
{
let isBarrier = 1;
}

//Unconditional jump with register PC:=DST
def JUMPREG : FJR<
(outs),
(ins GPR32:$cond),
"jmp $cond",
[(brind i32:$cond)],
0>
{
let isBranch = 1;
let isIndirectBranch = 1;
let isBarrier = 1;
}

// Return PC:=RA
def JRET : FJR<
(outs),
(ins),
"jret",
[(return)],
3>
{
let Inst{23-18} = 0;
let Inst{17-0} = 0;

let isReturn = 1;
let isTerminator = 1;
let isBarrier = 1;
}

//Conditional Branch
def BEQZ : FJR<
(outs),
(ins GPR32:$cond, brtarget:$addr),
"beqz $cond, $addr",
[],
5>;

//Conditional Branch
def BNEZ : FJR<
(outs),
(ins GPR32:$cond, brtarget:$addr),
"bnez $cond, $addr",
[],
6>;
}

let isCall = 1, Defs = [ RA_REG ] in {
//Jump with offset and save return address RA:=PC+4, PC:=PC+addr
def JMPSR_OFF : FJ<
(outs),
(ins calltarget:$addr, variable_ops),
"jmpsr $addr",
[],
1>;

//Jump with register and save return address RA:=PC+4, PC:=DST
def JMPSR_REG : FJR<
(outs),
(ins GPR32:$dst, variable_ops),
"jmpsr $dst",
[(call i32:$dst)],
1>
{
bits<6> dst;

let Inst{23-18} = dst;
}
}

//===----------------------------------------------------------------------===//
// Control Instructions (Format C)
//===----------------------------------------------------------------------===//

def BARRIER : FC<
(outs),
(ins GPR32:$src0, GPR32:$src1),
"barrier $src0, $src1",
[(int_npu_barrier i32:$src0, i32:$src1)],
0>;

def FLUSH : FC<
(outs),
(ins GPR32:$src0),
"flush $src0",
[(int_npu_flush i32:$src0)],
2>{
let Inst{17-12} = 0;
}

// READ Control Register
def READCR : FC<
(outs GPR32:$src0),
(ins GPR32:$src1),
"read_cr $src0, $src1",
[(set i32:$src0, (int_npu_read_control_reg i32:$src1))],
3>;

// WRITE Control Register
def WRITECR : FC<
(outs),
(ins GPR32:$src0, GPR32:$src1),
"write_cr $src0, $src1",
[(int_npu_write_control_reg i32:$src0, i32:$src1)],
4>;

//===----------------------------------------------------------------------===//
// Miscellaneous Instructions
//===----------------------------------------------------------------------===//

def NOP : InstNaplesPU<
(outs),
(ins),
"nop",
[]>
{
let Inst{31-0} = 0xffffffff;
}

def LOAD_EFFECTIVE_ADDR : InstNaplesPU<
(outs GPR32:$dst),
(ins LEAri:$addr),
"_lea $dst, $addr",
[(set i32:$dst, ADDRri:$addr)]> {

let isAsmParserOnly = 1; // Don't disassemble

bits<16> addr;
bits<6> dst;

let Inst{31-29} = 0b010;
let Inst{28-24} = 4;
let Inst{23-18} = dst;
let Inst{17-2} = addr;
let Inst{1} = 0;
let Inst{0} = 0;

}

//TODO: (Catello) Add symbol in NaplesPUAsmParser::ProcessInstruction.
// This node defines the lea pseudo-instruction that can be used in
// assembly files.
def LOAD_EFFECTIVE_ADDR_SYM : InstNaplesPU<
(outs GPR32:$dst),
(ins symref:$label),
"lea $dst, $label",
[]> {

let isPseudo = 1;

}

def LEAH : InstNaplesPU<
(outs GPR32:$dst),
(ins ABSh:$addr),
"leah $dst, $addr",
[]> {
let isAsmParserOnly = 1; // Don't disassemble

bits<16> addr;
bits<6> dst;

let Inst{31-27} = 0b01100; // Format MOVEI
let Inst{26-24} = 1; //Opcode MOVEI
let Inst{23-18} = dst;
let Inst{17-2} = addr;
let Inst{1} = 0;
let Inst{0} = 0;
}

def LEAL : InstNaplesPU<
(outs GPR32:$dst),
(ins GPR32:$addrh, ABSl:$addr),
"leal $dst, $addr",
[]> {
let isAsmParserOnly = 1; // Don't disassemble

//costraint used to let llvm use the same destination register as leah
let Constraints = "$dst = $addrh";

bits<16> addr;
bits<6> dst;

let Inst{31-27} = 0b01100; // Format MOVEI
let Inst{26-24} = 0; //Opcode MOVEI
let Inst{23-18} = dst;
let Inst{17-2} = addr;
let Inst{1} = 0;
let Inst{0} = 0;
}

//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//

// These pseudo ops capture outgoing argument space on the stack and will be removed
// by later passes.
let Defs = [ SP_REG ], Uses = [ SP_REG ], hasSideEffects = 1 in {
def ADJCALLSTACKDOWN : Pseudo<
(outs),
(ins i32imm:$amt1, i32imm:$amt2),
[(callseq_start timm:$amt1, timm:$amt2)]>;

def ADJCALLSTACKUP : Pseudo<
(outs),
(ins i32imm:$amt1, i32imm:$amt2),
[(callseq_end timm:$amt1, timm:$amt2)]>;
}

// SELECT pseudo instructions. This architecture doesn't actually have a scalar
// conditional move instruction. These will be replaced in a later pass
// with a diamond pattern of conditional branches.
//
let usesCustomInserter = 1 in {
def SELECTI : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$pred, GPR32:$true, GPR32:$false),
[(set i32:$dst, (selcondresult i32:$pred, i32:$true, i32:$false))]>;

def SELECTF : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$pred, GPR32:$true, GPR32:$false),
[(set f32:$dst, (selcondresult i32:$pred, f32:$true, f32:$false))]>;

def SELECTVI : Pseudo<
(outs VR512W:$dst),
(ins GPR32:$pred, VR512W:$true, VR512W:$false),
[(set v16i32:$dst, (selcondresult i32:$pred, v16i32:$true, v16i32:$false))]>;

def SELECTVF : Pseudo<
(outs VR512W:$dst),
(ins GPR32:$pred, VR512W:$true, VR512W:$false),
[(set v16f32:$dst, (selcondresult i32:$pred, v16f32:$true, v16f32:$false))]>;
}

let usesCustomInserter = 1 in {
def LoadI32 : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$val),
[(set i32:$dst, (i32 imm:$val))]>;

def LoadF32 : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$val),
[(set f32:$dst, (f32 fpimm:$val))]>;

}

let usesCustomInserter = 1 in {
def InsertELT32 : Pseudo<
(outs VR512W:$dst),
(ins VR512W:$vec, GPR32:$elem, GPR32:$pos),
[(set v16i32:$dst, (insert_elt v16i32:$vec, i32:$elem, i32:$pos))]>;

}

def : Pat <(v16f32 (insert_elt v16f32:$vec, f32:$elem, i32:$pos)), (v16f32 (InsertELT32 v16f32:$vec, f32:$elem, i32:$pos))>;

// Atomics
let usesCustomInserter = 1 in {
defm ATOMIC_LOAD_ADD : AtomicBinary<atomic_load_add>;
defm ATOMIC_LOAD_SUB : AtomicBinary<atomic_load_sub>;
defm ATOMIC_LOAD_AND : AtomicBinary<atomic_load_and>;
defm ATOMIC_LOAD_OR : AtomicBinary<atomic_load_or>;
defm ATOMIC_LOAD_XOR : AtomicBinary<atomic_load_xor>;
defm ATOMIC_LOAD_NAND : AtomicBinary<atomic_load_nand>;

def ATOMIC_CMP_SWAP : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, GPR32:$cmp, GPR32:$swap),
[(set i32:$dst, (atomic_cmp_swap GPR32:$ptr, GPR32:$cmp, GPR32:$swap))]>;

def ATOMIC_SWAP : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, GPR32:$swap),
[(set i32:$dst, (atomic_swap GPR32:$ptr, GPR32:$swap))]>;
}

//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//

// Shuffle patterns
def : Pat<(int_npu_shufflef32 v16f32:$src0, v16i32:$src1),
(SHUFFLEI_32 v16f32:$src0, v16i32:$src1)>;

// Splat patterns

def : Pat<(v16i32 (splat i32:$src0)), (MOVE_VS_32 i32:$src0)>;
def : Pat<(v16f32 (splat f32:$src0)), (MOVE_VS_32 f32:$src0)>;

def : Pat<(int_npu_vector_mixf32 v16f32:$src0, v16f32:$oldvalue),
(MOVE_VV_M_32 v16f32:$src0, v16f32:$oldvalue)>;

//---------------- Patterns for load and store ----------------//
//---------------- scalar load and store ----------------//
// zextload bool -> zextload byte
def : Pat<(i32 (zextloadi1_mem ADDRri:$addr)), (L32BU_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (zextloadi1_scratch ADDRri:$addr)), (L32BU_Scratchpad ADDRri:$addr)>;

//---------------- scalar extload->zextload ----------------//
// Scalar load to 32-bit registers
def : Pat<(i32 (extloadi1_mem ADDRri:$addr)), (L32BU_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (extloadi8_mem ADDRri:$addr)), (L32BU_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (extloadi16_mem ADDRri:$addr)), (L32SU_Mainmem ADDRri:$addr)>;
def : Pat<(f32 (MemLoad ADDRri:$addr)), (L32W_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (extloadi1_scratch ADDRri:$addr)), (L32BU_Scratchpad ADDRri:$addr)>;
def : Pat<(i32 (extloadi8_scratch ADDRri:$addr)), (L32BU_Scratchpad ADDRri:$addr)>;
def : Pat<(i32 (extloadi16_scratch ADDRri:$addr)), (L32SU_Scratchpad ADDRri:$addr)>;
def : Pat<(f32 (ScratchpadLoad ADDRri:$addr)), (L32W_Scratchpad ADDRri:$addr)>;

//---------------- scalar f32 load-> i32 load ----------------//
// Scalar store to 32-bit registers
def : Pat<(MemStore f32:$dstsrc, ADDRri:$addr), (S32W_Mainmem f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore f32:$dstsrc, ADDRri:$addr), (S32W_Scratchpad f32:$dstsrc, ADDRri:$addr)>;

//---------------- vector load and store ----------------//
//---------------- intrinsics load and store ----------------//
//integer
def : Pat<(v16i32 (int_npu_block_loadv16i8 ADDRri:$addr)), (v16i32 (LV32BMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16i8_scratchpad ADDRri:$addr)), (v16i32 (LV32BScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16u8 ADDRri:$addr)), (v16i32 (LV32BUMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16u8_scratchpad ADDRri:$addr)), (v16i32 (LV32BUScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16i16 ADDRri:$addr)), (v16i32 (LV32SMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16i16_scratchpad ADDRri:$addr)), (v16i32 (LV32SScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16u16 ADDRri:$addr)), (v16i32 (LV32SUMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16u16_scratchpad ADDRri:$addr)), (v16i32 (LV32SUScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_npu_block_loadv16i32_scratchpad ADDRri:$addr)), (v16i32 (LV32WScratchpad_U ADDRri:$addr))>;

def : Pat<(int_npu_block_storev16i8 ADDRri:$addr, v16i32:$dstsrc), (SV32BMainmem_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_npu_block_storev16i8_scratchpad ADDRri:$addr, v16i32:$dstsrc), (SV32BScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_npu_block_storev16i16 ADDRri:$addr, v16i32:$dstsrc), (SV32SMainmem_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_npu_block_storev16i16_scratchpad ADDRri:$addr, v16i32:$dstsrc), (SV32SScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_npu_block_storev16i32_scratchpad ADDRri:$addr, v16i32:$dstsrc), (SV32WScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;

//float
def : Pat<(v16f32 (int_npu_block_loadv16f32_scratchpad ADDRri:$addr)), (LV32WScratchpad_U ADDRri:$addr)>;
def : Pat<(v16f32 (int_npu_block_loadv16f32_masked ADDRri:$addr)), (LV32WMainmem_M ADDRri:$addr)>;
def : Pat<(v16f32 (int_npu_block_loadv16f32_scratchpad_masked ADDRri:$addr)), (LV32WScratchpad_M ADDRri:$addr)>;

def : Pat<(int_npu_block_storev16f32_scratchpad ADDRri:$addr, v16f32:$dstsrc), (SV32WScratchpad_U v16f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_npu_block_storev16f32_masked ADDRri:$addr, v16f32:$dstsrc), (SV32WMainmem_M v16f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_npu_block_storev16f32_scratchpad_masked ADDRri:$addr, v16f32:$dstsrc), (SV32WScratchpad_M v16f32:$dstsrc, ADDRri:$addr)>;

// Float gather/scatter
def : Pat<(int_npu_gather_loadf32_scratchpad V16ADDRri:$addr), (GLV32WScratchpad_U V16ADDRri:$addr)>;
def : Pat<(int_npu_gather_loadf32_scratchpad_masked V16ADDRri:$addr), (GLV32WScratchpad_M V16ADDRri:$addr)>;

def : Pat<(int_npu_scatter_storef32_scratchpad V16ADDRri:$addr, v16f32:$srcDest), (SSV32WScratchpad_U v16f32:$srcDest, V16ADDRri:$addr)>;
def : Pat<(int_npu_scatter_storef32_scratchpad_masked V16ADDRri:$addr, v16f32:$srcDest), (SSV32WScratchpad_M v16f32:$srcDest, V16ADDRri:$addr)>;

//---------------- vector anyextload -> sextload ----------------//
def : Pat<(v16i32 (anyextloadv16i8_mem ADDRri:$addr)), (LV32BMainmem_U ADDRri:$addr)>;
def : Pat<(v16i32 (anyextloadv16i8_scratch ADDRri:$addr)), (LV32BScratchpad_U ADDRri:$addr)>;
def : Pat<(v16i32 (anyextloadv16i16_mem ADDRri:$addr)), (LV32SMainmem_U ADDRri:$addr)>;
def : Pat<(v16i32 (anyextloadv16i16_scratch ADDRri:$addr)), (LV32SScratchpad_U ADDRri:$addr)>;

//---------------- vector load/store -> sextload/truncstore ----------------//
def : Pat<(v16i8 (MemLoad ADDRri:$addr)), (LV32BMainmem_U ADDRri:$addr)>;
def : Pat<(v16i8 (ScratchpadLoad ADDRri:$addr)), (LV32BScratchpad_U ADDRri:$addr)>;
def : Pat<(v16i16 (MemLoad ADDRri:$addr)), (LV32SMainmem_U ADDRri:$addr)>;
def : Pat<(v16i16 (ScratchpadLoad ADDRri:$addr)), (LV32SScratchpad_U ADDRri:$addr)>;
def : Pat<(v16i32 (ScratchpadLoad ADDRri:$addr)), (LV32WScratchpad_U ADDRri:$addr)>;

def : Pat<(MemStore v16i8:$dstsrc, ADDRri:$addr), (SV32BMainmem_U v16i8:$dstsrc, ADDRri:$addr)>;
def : Pat<(MemStore v16i16:$dstsrc, ADDRri:$addr), (SV32SMainmem_U v16i16:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16i8:$dstsrc, ADDRri:$addr), (SV32BScratchpad_U v16i8:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16i16:$dstsrc, ADDRri:$addr), (SV32SScratchpad_U v16i16:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16i32:$dstsrc, ADDRri:$addr), (SV32WScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;

def : Pat<(v16f32 (MemLoad ADDRri:$addr)), (LV32WMainmem_U ADDRri:$addr)>;
def : Pat<(v16f32 (ScratchpadLoad ADDRri:$addr)), (LV32WScratchpad_U ADDRri:$addr)>;

def : Pat<(MemStore v16f32:$dstsrc, ADDRri:$addr), (SV32WMainmem_U v16f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16f32:$dstsrc, ADDRri:$addr), (SV32WScratchpad_U v16f32:$dstsrc, ADDRri:$addr)>;

// Questi pattern servono per gestire i tipi di dato vettoriali di dim < 512 bits
// v16i8 <=> v16i32
def : Pat<(v16i32 (bitconvert v16i8:$src)), (v16i32 (SEXT8_32VV_U v16i8:$src))>;
def : Pat<(MemStore (v16i8 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32BMainmem_U v16i32:$src, ADDRri:$addr)>;
def : Pat<(ScratchpadStore (v16i8 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32BScratchpad_U v16i32:$src, ADDRri:$addr)>;
// v16i16 <=> v16i32
def : Pat<(v16i32 (bitconvert v16i16:$src)), (v16i32 (SEXT16_32VV_U v16i16:$src))>;
def : Pat<(MemStore (v16i16 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32SMainmem_U v16i32:$src, ADDRri:$addr)>;
def : Pat<(ScratchpadStore (v16i16 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32SScratchpad_U v16i32:$src, ADDRri:$addr)>;

// v8f32 <=> v16f32
//def : Pat<(MemStore (v8f32 (extract_subvector v16f32:$src, (i32 0))), ADDRri:$addr), (SV32WMainmem_U v16f32:$src, ADDRri:$addr)>;
//def : Pat<(ScratchpadStore (v8f32 (extract_subvector v16f32:$src, (i32 0))), ADDRri:$addr), (SV32WScratchpad_U v16f32:$src, ADDRri:$addr)>;

//---------------- Patterns for type conversions ----------------//

// Sign Extension Patterns sext_inreg -> sext
def : Pat<(v16i32 (sext_inreg v16i32:$src, v16i8)), (v16i32 (SEXT8_32VV_U v16i32:$src))>;
def : Pat<(v16i32 (sext_inreg v16i32:$src, v16i16)), (v16i32 (SEXT16_32VV_U v16i32:$src))>;

// BITCAST patterns
def : Pat<(f32 (bitconvert (i32 GPR32:$src))), (f32 GPR32:$src)>;
def : Pat<(i32 (bitconvert (f32 GPR32:$src))), (i32 GPR32:$src)>;
def : Pat<(v16f32 (bitconvert (v16i32 VR512W:$src))), (v16f32 VR512W:$src)>;
def : Pat<(v16i32 (bitconvert (v16f32 VR512W:$src))), (v16i32 VR512W:$src)>;

// CLZ and CTZ Intrinsics
def : Pat<(i32 (int_npu_clzi32 i32:$src)),
(i32 (CLZSS_32 i32:$src))>;
def : Pat<(v16i32 (int_npu_clzv16i32 v16i32:$src)),
(v16i32 (CLZVV_U_32 v16i32:$src))>;

def : Pat<(i32 (int_npu_ctzi32 i32:$src)),
(i32 (CTZSS_32 i32:$src))>;

def : Pat<(v16i32 (int_npu_ctzv16i32 v16i32:$src)),
(v16i32 (CTZVV_U_32 v16i32:$src))>;

// Integer division
// v16i32
def : Pat<(v16i32 (sdiv v16i32:$src1, v16i32:$src2)),
(F32TOI32_VV_U (DIVFVVV_U_32 (I32TOF32_VV_U v16i32:$src1), (I32TOF32_VV_U v16i32:$src2)))>;

// Branch patterns
def : Pat<(brcond (i32 (setne i32:$lhs, 0)), bb:$addr), (BNEZ i32:$lhs, bb:$addr)>;
def : Pat<(brcond (i32 (seteq i32:$lhs, 0)), bb:$addr), (BEQZ i32:$lhs, bb:$addr)>;
def : Pat<(brcond i32:$lhs, bb:$addr), (BNEZ i32:$lhs, bb:$addr)>;

// Call patterns
def : Pat<(call tglobaladdr:$addr), (JMPSR_OFF tglobaladdr:$addr)>;
def : Pat<(call texternalsym:$addr), (JMPSR_OFF texternalsym:$addr)>;

// GetLane patterns
def : Pat<(extractelt v16f32:$src0, i32:$src1),
(GET_LANEI_32 v16f32:$src0, i32:$src1)>;
def : Pat<(extractelt v16f32:$src, simm9:$imm),
(GET_LANEIimm v16f32:$src, imm:$imm)>;

// ISD Nodes Patterns
def : Pat<(i32 (leah tglobaladdr:$addr)), (LEAH tglobaladdr:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tglobaladdr:$addr)), (LEAL i32:$addrh, tglobaladdr:$addr)>;
def : Pat<(i32 (leah tconstpool:$addr)), (LEAH tconstpool:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tconstpool:$addr)), (LEAL i32:$addrh, tconstpool:$addr)>;
def : Pat<(i32 (leah tblockaddress:$addr)), (LEAH tblockaddress:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tblockaddress:$addr)), (LEAL i32:$addrh, tblockaddress:$addr)>;
def : Pat<(i32 (leah tjumptable:$addr)), (LEAH tjumptable:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tjumptable:$addr)), (LEAL i32:$addrh, tjumptable:$addr)>;
</syntaxhighlight>

NaplesPUInstrInfo.td

2019-06-21T15:01:52Z

Francesco: Francesco moved page NuPlusInstrInfo.td to NaplesPUInstrInfo.td

[[Category:Tablegen Files]]
NuPlusInstrInfo.td and [[NuPlusInstrFormats.td]] describe the nu+ instructions and the patterns to transform LLVM IR into machine code. The NuPlusInstrInfo.td contains the instructions definition and the patterns necessary for the translation from the LLVM IR to the nu+ machine code.

<syntaxhighlight>
//===-- NuPlusInstrInfo.td - Target Description for NuPlus Target -----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the NuPlus instructions in TableGen format.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//

include "NuPlusInstrFormats.td"

//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Arithmetic Instructions (Format R & I)
//===----------------------------------------------------------------------===//

//Arithmetic Integer Two operands
defm OR : FArithInt_TwoOp<"or", or, 1>;
defm AND : FArithInt_TwoOp<"and", and, 2>;
defm XOR : FArithInt_TwoOp<"xor", xor, 3>;
defm ADD : FArithInt_TwoOp<"add", add, 4>;
defm SUB : FArithInt_TwoOp<"sub", sub, 5>;
defm MULL : FArithInt_TwoOp<"mull", mul, 6>;
defm MULH : FArithInt_TwoOp<"mulhs", mulhs, 7>;
defm MULHU : FArithInt_TwoOp<"mulhu", mulhu, 8>;
defm SRA : FSRInt_TwoOp<"ashr", sra, 9>;
defm SRL : FSRInt_TwoOp<"shr", srl, 10>;
defm SLL : FSRInt_TwoOp<"shl", shl, 11>;
//Arithmetic Integer One operand
defm CLZ : FArithInt_OneOp<"clz", ctlz, 12>;
defm CTZ : FArithInt_OneOp<"ctz", cttz, 13>;
//Compare Integer
defm SEQSI : FCompInt<"cmpeq", SETEQ, 14, int_nuplus_mask_cmpi32_eq>;//, int_nuplus_mask_cmpi64_eq>;
defm SNESI : FCompInt<"cmpne", SETNE, 15, int_nuplus_mask_cmpi32_ne>;//, int_nuplus_mask_cmpi64_ne>;
defm SGTSI : FCompInt<"cmpgt", SETGT, 16, int_nuplus_mask_cmpi32_sgt>;//, int_nuplus_mask_cmpi64_sgt>;
defm SGESI : FCompInt<"cmpge", SETGE, 17, int_nuplus_mask_cmpi32_sge>;//, int_nuplus_mask_cmpi64_sge>;
defm SLTSI : FCompInt<"cmplt", SETLT, 18, int_nuplus_mask_cmpi32_slt>;//, int_nuplus_mask_cmpi64_slt>;
defm SLESI : FCompInt<"cmple", SETLE, 19, int_nuplus_mask_cmpi32_sle>;//, int_nuplus_mask_cmpi64_sle>;
//Compare Unsigned
defm SGTUI : FCompInt<"cmpugt", SETUGT, 20, int_nuplus_mask_cmpi32_ugt>;//, int_nuplus_mask_cmpi64_ugt>;
defm SGEUI : FCompInt<"cmpuge", SETUGE, 21, int_nuplus_mask_cmpi32_uge>;//, int_nuplus_mask_cmpi64_uge>;
defm SLTUI : FCompInt<"cmpult", SETULT, 22, int_nuplus_mask_cmpi32_ult>;//, int_nuplus_mask_cmpi64_ult>;
defm SLEUI : FCompInt<"cmpule", SETULE, 23, int_nuplus_mask_cmpi32_ule>;//, int_nuplus_mask_cmpi64_ule>;

//Cross Product Instruction
def CROSSPROD_32 : FR_TwoOp_Unmasked_32 <
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
"crp $dst, $src0, $src1",
[(set v16i32:$dst, (int_nuplus_crossprodv16i32 v16i32:$src0, v16i32:$src1))],
63,
Fmt_V,
Fmt_V,
Fmt_V>;

//Shuffle
def SHUFFLEI_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
"shuffle_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (int_nuplus_shufflei32 v16i32:$src0, v16i32:$src1))],
24,
Fmt_V,
Fmt_V,
Fmt_V>;

//Get lane
def GET_LANEI_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, GPR32:$src1),
"getlane_i32 $dst, $src0, $src1",
[(set i32:$dst, (extractelt v16i32:$src0, i32:$src1))],
25,
Fmt_S,
Fmt_V,
Fmt_S>;

def GET_LANEIimm : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
"getlanei $dst, $src, $imm",
[(set i32:$dst, (extractelt v16i32:$src, simm9:$imm))],
25,
Fmt_S,
Fmt_V>;

//Move register - register
def MOVE_SS_32 : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
"move_i32 $dst, $src0",
[],
32,
Fmt_S,
Fmt_S>;

def MOVE_VS_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins GPR32:$src0),
"move_i32 $dst, $src0",
[(set v16i32:$dst, (splat i32:$src0))],
32,
Fmt_V,
Fmt_S>;

def MOVE_VV_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
"move_i32 $dst, $src0",
[],
32,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue", isAsmParserOnly=1 in {

def MOVE_VS_M_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins GPR32:$src0, VR512W:$oldvalue),
"move_i32 $dst, $src0",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (splat i32:$src0), v16i32:$oldvalue))],
32,
Fmt_V,
Fmt_S>;

def MOVE_VV_M_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
"move_i32 $dst, $src0",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 v16i32:$src0, v16i32:$oldvalue))],
32,
Fmt_V,
Fmt_V>;

}

//Arithmetic Float Two operands
defm ADDF : FArithFloat_TwoOp<"fadd", fadd, 33>;
defm SUBF : FArithFloat_TwoOp<"fsub", fsub, 34>;
defm MULF : FArithFloat_TwoOp<"fmul", fmul, 35>;
defm DIVF : FArithFloat_TwoOp<"fdiv", fdiv, 36>;
//Compare Float
def FloatCompareType: SDTypeProfile<1, 2, [
SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>
]>;
def FGT: SDNode<"NuPlusISD::FGT", FloatCompareType>;
def FGE: SDNode<"NuPlusISD::FGE", FloatCompareType>;
def FLT: SDNode<"NuPlusISD::FLT", FloatCompareType>;
def FLE: SDNode<"NuPlusISD::FLE", FloatCompareType>;
def FEQ: SDNode<"NuPlusISD::FEQ", FloatCompareType>;
def FNE: SDNode<"NuPlusISD::FNE", FloatCompareType>;

defm SEQFO : FCompFloat<"cmpfeq", FEQ, 37, int_nuplus_mask_cmpf32_eq>;//, int_nuplus_mask_cmpf64_eq>;
defm SNEFO : FCompFloat<"cmpfne", FNE, 38, int_nuplus_mask_cmpf32_ne>;//, int_nuplus_mask_cmpf64_ne>;
defm SGTFO : FCompFloat<"cmpfgt", FGT, 39, int_nuplus_mask_cmpf32_gt>;//, int_nuplus_mask_cmpf64_gt>;
defm SGEFO : FCompFloat<"cmpfge", FGE, 40, int_nuplus_mask_cmpf32_ge>;//, int_nuplus_mask_cmpf64_ge>;
defm SLTFO : FCompFloat<"cmpflt", FLT, 41, int_nuplus_mask_cmpf32_lt>;//, int_nuplus_mask_cmpf64_lt>;
defm SLEFO : FCompFloat<"cmpfle", FLE, 42, int_nuplus_mask_cmpf32_le>;//, int_nuplus_mask_cmpf64_le>;

//sign extension
defm SEXT8_32 : FSext_32<"sext8", i8, 43, v16i8>;
defm SEXT16_32 : FSext_32<"sext16", i16, 44, v16i16>;

//Integer to Float conversion
def I32TOF32_SS : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
"itof_i32 $dst, $src0",
[(set f32:$dst, (sint_to_fp i32:$src0))],
48,
Fmt_S,
Fmt_S>;

def I32TOF32_VV_U : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
"itof_i32 $dst, $src0",
[(set v16f32:$dst, (sint_to_fp v16i32:$src0))],
48,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
def I32TOF32_VV_M : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
"itof_i32.m $dst, $src0",
[(set v16f32:$dst, (int_nuplus_vector_mixf32 (sint_to_fp v16i32:$src0), v16f32:$oldvalue))],
48,
Fmt_V,
Fmt_V>;

}

//Float to Integer conversion
def F32TOI32_SS : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
"ftoi_i32 $dst, $src0",
[(set i32:$dst, (fp_to_sint f32:$src0))],
49,
Fmt_S,
Fmt_S>;

def F32TOI32_VV_U : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
"ftoi_i32 $dst, $src0",
[(set v16i32:$dst, (fp_to_sint v16f32:$src0))],
49,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
def F32TOI32_VV_M : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
"ftoi_i32.m $dst, $src0",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (fp_to_sint v16f32:$src0), v16i32:$oldvalue))],
49,
Fmt_V,
Fmt_V>;

}

//===----------------------------------------------------------------------===//
// MOVEI Instructions (Format MOVEI)
//===----------------------------------------------------------------------===//

defm MOVEIL : FMOVEI_ALL<"moveil", 0>;
defm MOVEIH : FMOVEI_ALL<"moveih", 1>;
defm MOVEI : FMOVEI_ALL<"movei", 2>;

//===----------------------------------------------------------------------===//
// LOAD/STORE SPECIAL REGISTERS
//===----------------------------------------------------------------------===//

def READMR : READ_SPR<MaskReg, "read_mr", int_nuplus_read_mask_reg>;
def WRITEMR : WRITE_SPR<MaskReg, "write_mr", int_nuplus_write_mask_reg>;

//Create Mask Instruction
def CREATEMASK_32 : FR_OneOp_Unmasked_32 <
(outs GPR32:$dst),
(ins VR512W:$src0),
"crt_mask_i32 $dst, $src0",
[(set i32:$dst, (int_nuplus_createmaskv16i32 v16i32:$src0))],
50,
Fmt_S,
Fmt_V>;

//===----------------------------------------------------------------------===//
// MEM Instructions (Format M)
//===----------------------------------------------------------------------===//

// Scalar load to 32-bit registers
defm L32BS : FMLoadScalar_32<"_s8", sextloadi8_mem, sextloadi8_scratch, 0>;
defm L32SS : FMLoadScalar_32<"_s16", sextloadi16_mem, sextloadi16_scratch, 1>;
defm L32W : FMLoadScalar_32<"", MemLoad, ScratchpadLoad, 2>;
defm L32BU : FMLoadScalar_32<"_u8", zextloadi8_mem, zextloadi8_scratch, 4>;
defm L32SU : FMLoadScalar_32<"_u16", zextloadi16_mem, zextloadi16_scratch, 5>;
defm S32B : FMStoreScalar_32<"_8", truncstorei8_mem, truncstorei8_scratch, 32>;
defm S32S : FMStoreScalar_32<"_16", truncstorei16_mem, truncstorei16_scratch, 33>;
defm S32W : FMStoreScalar_32<"", MemStore, ScratchpadStore, 34>;
//--------------------------------------------------------------------------------//
//Vector load block
//--------------------------------------------------------------------------------//

// Vector load to 32-bit registers
defm LV32B : FMLoadVector_32<"_v16i8", sextloadv16i8_mem, sextloadv16i8_scratch,
int_nuplus_block_loadv16i8_masked, int_nuplus_block_loadv16i8_scratchpad_masked,
7>;
defm LV32S : FMLoadVector_32<"_v16i16", sextloadv16i16_mem, sextloadv16i16_scratch,
int_nuplus_block_loadv16i16_masked, int_nuplus_block_loadv16i16_scratchpad_masked,
8>;
defm LV32W : FMLoadVector_32<"_v16i32", MemLoad, ScratchpadLoad,
int_nuplus_block_loadv16i32_masked, int_nuplus_block_loadv16i32_scratchpad_masked,
9>;

defm LV32BU : FMLoadVector_32<"_v16u8", zextloadv16i8_mem, zextloadv16i8_scratch,
int_nuplus_block_loadv16u8_masked, int_nuplus_block_loadv16u8_scratchpad_masked,
11>;
defm LV32SU : FMLoadVector_32<"_v16u16", zextloadv16i16_mem, zextloadv16i16_scratch,
int_nuplus_block_loadv16u16_masked, int_nuplus_block_loadv16u16_scratchpad_masked,
12>;
//--------------------------------------------------------------------------------//
//Vector load gather
//--------------------------------------------------------------------------------//

// Vector gather to 32-bit registers
defm GLV32W : FMGather_32<"32", int_nuplus_gather_loadi32_scratchpad,
int_nuplus_gather_loadi32_scratchpad_masked,
16>;

//--------------------------------------------------------------------------------//
//Vector store block
//--------------------------------------------------------------------------------//

// Vector store from 32-bit registers
defm SV32B : FMStoreVector_32<"_v16i8", truncstorev16i8_mem, truncstorev16i8_scratch,
int_nuplus_block_storev16i8_masked, int_nuplus_block_storev16i8_scratchpad_masked,
36>;
defm SV32S : FMStoreVector_32<"_v16i16", truncstorev16i16_mem, truncstorev16i16_scratch,
int_nuplus_block_storev16i16_masked, int_nuplus_block_storev16i16_scratchpad_masked,
37>;
defm SV32W : FMStoreVector_32<"_v16i32", MemStore, ScratchpadStore,
int_nuplus_block_storev16i32_masked, int_nuplus_block_storev16i32_scratchpad_masked,
38>;

//--------------------------------------------------------------------------------//
//Vector store scatter
//--------------------------------------------------------------------------------//

// Vector scatter from 32-bit registers
defm SSV32W : FMScatter_32<"32",int_nuplus_scatter_storei32_scratchpad,
int_nuplus_scatter_storei32_scratchpad_masked,
42>;

//===----------------------------------------------------------------------===//
// Jump and Branch Instructions (Format J/JR)
//===----------------------------------------------------------------------===//

let isTerminator = 1 in {
//Unconditional jump with offset, PC:=PC+addr
def JMP : FJ<
(outs),
(ins brtarget:$addr),
"jmp $addr",
[(br bb:$addr)],
0>
{
let isBarrier = 1;
}

//Unconditional jump with register PC:=DST
def JUMPREG : FJR<
(outs),
(ins GPR32:$cond),
"jmp $cond",
[(brind i32:$cond)],
0>
{
let isBranch = 1;
let isIndirectBranch = 1;
let isBarrier = 1;
}

// Return PC:=RA
def JRET : FJR<
(outs),
(ins),
"jret",
[(return)],
3>
{
let Inst{23-18} = 0;
let Inst{17-0} = 0;

let isReturn = 1;
let isTerminator = 1;
let isBarrier = 1;
}

//Conditional Branch
def BEQZ : FJR<
(outs),
(ins GPR32:$cond, brtarget:$addr),
"beqz $cond, $addr",
[],
5>;

//Conditional Branch
def BNEZ : FJR<
(outs),
(ins GPR32:$cond, brtarget:$addr),
"bnez $cond, $addr",
[],
6>;
}

let isCall = 1, Defs = [ RA_REG ] in {
//Jump with offset and save return address RA:=PC+4, PC:=PC+addr
def JMPSR_OFF : FJ<
(outs),
(ins calltarget:$addr, variable_ops),
"jmpsr $addr",
[],
1>;

//Jump with register and save return address RA:=PC+4, PC:=DST
def JMPSR_REG : FJR<
(outs),
(ins GPR32:$dst, variable_ops),
"jmpsr $dst",
[(call i32:$dst)],
1>
{
bits<6> dst;

let Inst{23-18} = dst;
}
}

//===----------------------------------------------------------------------===//
// Control Instructions (Format C)
//===----------------------------------------------------------------------===//

def BARRIER : FC<
(outs),
(ins GPR32:$src0, GPR32:$src1),
"barrier $src0, $src1",
[(int_nuplus_barrier i32:$src0, i32:$src1)],
0>;

def FLUSH : FC<
(outs),
(ins GPR32:$src0),
"flush $src0",
[(int_nuplus_flush i32:$src0)],
2>{
let Inst{17-12} = 0;
}

// READ Control Register
def READCR : FC<
(outs GPR32:$src0),
(ins GPR32:$src1),
"read_cr $src0, $src1",
[(set i32:$src0, (int_nuplus_read_control_reg i32:$src1))],
3>;

// WRITE Control Register
def WRITECR : FC<
(outs),
(ins GPR32:$src0, GPR32:$src1),
"write_cr $src0, $src1",
[(int_nuplus_write_control_reg i32:$src0, i32:$src1)],
4>;

//===----------------------------------------------------------------------===//
// Miscellaneous Instructions
//===----------------------------------------------------------------------===//

def NOP : InstNuPlus<
(outs),
(ins),
"nop",
[]>
{
let Inst{31-0} = 0xffffffff;
}

def LOAD_EFFECTIVE_ADDR : InstNuPlus<
(outs GPR32:$dst),
(ins LEAri:$addr),
"_lea $dst, $addr",
[(set i32:$dst, ADDRri:$addr)]> {

let isAsmParserOnly = 1; // Don't disassemble

bits<16> addr;
bits<6> dst;

let Inst{31-29} = 0b010;
let Inst{28-24} = 4;
let Inst{23-18} = dst;
let Inst{17-2} = addr;
let Inst{1} = 0;
let Inst{0} = 0;

}

//TODO: (Catello) Add symbol in NuPlusAsmParser::ProcessInstruction.
// This node defines the lea pseudo-instruction that can be used in
// assembly files.
def LOAD_EFFECTIVE_ADDR_SYM : InstNuPlus<
(outs GPR32:$dst),
(ins symref:$label),
"lea $dst, $label",
[]> {

let isPseudo = 1;

}

def LEAH : InstNuPlus<
(outs GPR32:$dst),
(ins ABSh:$addr),
"leah $dst, $addr",
[]> {
let isAsmParserOnly = 1; // Don't disassemble

bits<16> addr;
bits<6> dst;

let Inst{31-27} = 0b01100; // Format MOVEI
let Inst{26-24} = 1; //Opcode MOVEI
let Inst{23-18} = dst;
let Inst{17-2} = addr;
let Inst{1} = 0;
let Inst{0} = 0;
}

def LEAL : InstNuPlus<
(outs GPR32:$dst),
(ins GPR32:$addrh, ABSl:$addr),
"leal $dst, $addr",
[]> {
let isAsmParserOnly = 1; // Don't disassemble

//costraint used to let llvm use the same destination register as leah
let Constraints = "$dst = $addrh";

bits<16> addr;
bits<6> dst;

let Inst{31-27} = 0b01100; // Format MOVEI
let Inst{26-24} = 0; //Opcode MOVEI
let Inst{23-18} = dst;
let Inst{17-2} = addr;
let Inst{1} = 0;
let Inst{0} = 0;
}

//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//

// These pseudo ops capture outgoing argument space on the stack and will be removed
// by later passes.
let Defs = [ SP_REG ], Uses = [ SP_REG ], hasSideEffects = 1 in {
def ADJCALLSTACKDOWN : Pseudo<
(outs),
(ins i32imm:$amt1, i32imm:$amt2),
[(callseq_start timm:$amt1, timm:$amt2)]>;

def ADJCALLSTACKUP : Pseudo<
(outs),
(ins i32imm:$amt1, i32imm:$amt2),
[(callseq_end timm:$amt1, timm:$amt2)]>;
}

// SELECT pseudo instructions. This architecture doesn't actually have a scalar
// conditional move instruction. These will be replaced in a later pass
// with a diamond pattern of conditional branches.
//
let usesCustomInserter = 1 in {
def SELECTI : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$pred, GPR32:$true, GPR32:$false),
[(set i32:$dst, (selcondresult i32:$pred, i32:$true, i32:$false))]>;

def SELECTF : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$pred, GPR32:$true, GPR32:$false),
[(set f32:$dst, (selcondresult i32:$pred, f32:$true, f32:$false))]>;

def SELECTVI : Pseudo<
(outs VR512W:$dst),
(ins GPR32:$pred, VR512W:$true, VR512W:$false),
[(set v16i32:$dst, (selcondresult i32:$pred, v16i32:$true, v16i32:$false))]>;

def SELECTVF : Pseudo<
(outs VR512W:$dst),
(ins GPR32:$pred, VR512W:$true, VR512W:$false),
[(set v16f32:$dst, (selcondresult i32:$pred, v16f32:$true, v16f32:$false))]>;
}

let usesCustomInserter = 1 in {
def LoadI32 : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$val),
[(set i32:$dst, (i32 imm:$val))]>;

def LoadF32 : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$val),
[(set f32:$dst, (f32 fpimm:$val))]>;

}

let usesCustomInserter = 1 in {
def InsertELT32 : Pseudo<
(outs VR512W:$dst),
(ins VR512W:$vec, GPR32:$elem, GPR32:$pos),
[(set v16i32:$dst, (insert_elt v16i32:$vec, i32:$elem, i32:$pos))]>;

}

def : Pat <(v16f32 (insert_elt v16f32:$vec, f32:$elem, i32:$pos)), (v16f32 (InsertELT32 v16f32:$vec, f32:$elem, i32:$pos))>;

// Atomics
let usesCustomInserter = 1 in {
defm ATOMIC_LOAD_ADD : AtomicBinary<atomic_load_add>;
defm ATOMIC_LOAD_SUB : AtomicBinary<atomic_load_sub>;
defm ATOMIC_LOAD_AND : AtomicBinary<atomic_load_and>;
defm ATOMIC_LOAD_OR : AtomicBinary<atomic_load_or>;
defm ATOMIC_LOAD_XOR : AtomicBinary<atomic_load_xor>;
defm ATOMIC_LOAD_NAND : AtomicBinary<atomic_load_nand>;

def ATOMIC_CMP_SWAP : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, GPR32:$cmp, GPR32:$swap),
[(set i32:$dst, (atomic_cmp_swap GPR32:$ptr, GPR32:$cmp, GPR32:$swap))]>;

def ATOMIC_SWAP : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, GPR32:$swap),
[(set i32:$dst, (atomic_swap GPR32:$ptr, GPR32:$swap))]>;
}

//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//

// Shuffle patterns
def : Pat<(int_nuplus_shufflef32 v16f32:$src0, v16i32:$src1),
(SHUFFLEI_32 v16f32:$src0, v16i32:$src1)>;

// Splat patterns

def : Pat<(v16i32 (splat i32:$src0)), (MOVE_VS_32 i32:$src0)>;
def : Pat<(v16f32 (splat f32:$src0)), (MOVE_VS_32 f32:$src0)>;

def : Pat<(int_nuplus_vector_mixf32 v16f32:$src0, v16f32:$oldvalue),
(MOVE_VV_M_32 v16f32:$src0, v16f32:$oldvalue)>;

//---------------- Patterns for load and store ----------------//
//---------------- scalar load and store ----------------//
// zextload bool -> zextload byte
def : Pat<(i32 (zextloadi1_mem ADDRri:$addr)), (L32BU_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (zextloadi1_scratch ADDRri:$addr)), (L32BU_Scratchpad ADDRri:$addr)>;

//---------------- scalar extload->zextload ----------------//
// Scalar load to 32-bit registers
def : Pat<(i32 (extloadi1_mem ADDRri:$addr)), (L32BU_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (extloadi8_mem ADDRri:$addr)), (L32BU_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (extloadi16_mem ADDRri:$addr)), (L32SU_Mainmem ADDRri:$addr)>;
def : Pat<(f32 (MemLoad ADDRri:$addr)), (L32W_Mainmem ADDRri:$addr)>;
def : Pat<(i32 (extloadi1_scratch ADDRri:$addr)), (L32BU_Scratchpad ADDRri:$addr)>;
def : Pat<(i32 (extloadi8_scratch ADDRri:$addr)), (L32BU_Scratchpad ADDRri:$addr)>;
def : Pat<(i32 (extloadi16_scratch ADDRri:$addr)), (L32SU_Scratchpad ADDRri:$addr)>;
def : Pat<(f32 (ScratchpadLoad ADDRri:$addr)), (L32W_Scratchpad ADDRri:$addr)>;

//---------------- scalar f32 load-> i32 load ----------------//
// Scalar store to 32-bit registers
def : Pat<(MemStore f32:$dstsrc, ADDRri:$addr), (S32W_Mainmem f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore f32:$dstsrc, ADDRri:$addr), (S32W_Scratchpad f32:$dstsrc, ADDRri:$addr)>;

//---------------- vector load and store ----------------//
//---------------- intrinsics load and store ----------------//
//integer
def : Pat<(v16i32 (int_nuplus_block_loadv16i8 ADDRri:$addr)), (v16i32 (LV32BMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16i8_scratchpad ADDRri:$addr)), (v16i32 (LV32BScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16u8 ADDRri:$addr)), (v16i32 (LV32BUMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16u8_scratchpad ADDRri:$addr)), (v16i32 (LV32BUScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16i16 ADDRri:$addr)), (v16i32 (LV32SMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16i16_scratchpad ADDRri:$addr)), (v16i32 (LV32SScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16u16 ADDRri:$addr)), (v16i32 (LV32SUMainmem_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16u16_scratchpad ADDRri:$addr)), (v16i32 (LV32SUScratchpad_U ADDRri:$addr))>;
def : Pat<(v16i32 (int_nuplus_block_loadv16i32_scratchpad ADDRri:$addr)), (v16i32 (LV32WScratchpad_U ADDRri:$addr))>;

def : Pat<(int_nuplus_block_storev16i8 ADDRri:$addr, v16i32:$dstsrc), (SV32BMainmem_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_nuplus_block_storev16i8_scratchpad ADDRri:$addr, v16i32:$dstsrc), (SV32BScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_nuplus_block_storev16i16 ADDRri:$addr, v16i32:$dstsrc), (SV32SMainmem_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_nuplus_block_storev16i16_scratchpad ADDRri:$addr, v16i32:$dstsrc), (SV32SScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_nuplus_block_storev16i32_scratchpad ADDRri:$addr, v16i32:$dstsrc), (SV32WScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;

//float
def : Pat<(v16f32 (int_nuplus_block_loadv16f32_scratchpad ADDRri:$addr)), (LV32WScratchpad_U ADDRri:$addr)>;
def : Pat<(v16f32 (int_nuplus_block_loadv16f32_masked ADDRri:$addr)), (LV32WMainmem_M ADDRri:$addr)>;
def : Pat<(v16f32 (int_nuplus_block_loadv16f32_scratchpad_masked ADDRri:$addr)), (LV32WScratchpad_M ADDRri:$addr)>;

def : Pat<(int_nuplus_block_storev16f32_scratchpad ADDRri:$addr, v16f32:$dstsrc), (SV32WScratchpad_U v16f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_nuplus_block_storev16f32_masked ADDRri:$addr, v16f32:$dstsrc), (SV32WMainmem_M v16f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(int_nuplus_block_storev16f32_scratchpad_masked ADDRri:$addr, v16f32:$dstsrc), (SV32WScratchpad_M v16f32:$dstsrc, ADDRri:$addr)>;

// Float gather/scatter
def : Pat<(int_nuplus_gather_loadf32_scratchpad V16ADDRri:$addr), (GLV32WScratchpad_U V16ADDRri:$addr)>;
def : Pat<(int_nuplus_gather_loadf32_scratchpad_masked V16ADDRri:$addr), (GLV32WScratchpad_M V16ADDRri:$addr)>;

def : Pat<(int_nuplus_scatter_storef32_scratchpad V16ADDRri:$addr, v16f32:$srcDest), (SSV32WScratchpad_U v16f32:$srcDest, V16ADDRri:$addr)>;
def : Pat<(int_nuplus_scatter_storef32_scratchpad_masked V16ADDRri:$addr, v16f32:$srcDest), (SSV32WScratchpad_M v16f32:$srcDest, V16ADDRri:$addr)>;

//---------------- vector anyextload -> sextload ----------------//
def : Pat<(v16i32 (anyextloadv16i8_mem ADDRri:$addr)), (LV32BMainmem_U ADDRri:$addr)>;
def : Pat<(v16i32 (anyextloadv16i8_scratch ADDRri:$addr)), (LV32BScratchpad_U ADDRri:$addr)>;
def : Pat<(v16i32 (anyextloadv16i16_mem ADDRri:$addr)), (LV32SMainmem_U ADDRri:$addr)>;
def : Pat<(v16i32 (anyextloadv16i16_scratch ADDRri:$addr)), (LV32SScratchpad_U ADDRri:$addr)>;

//---------------- vector load/store -> sextload/truncstore ----------------//
def : Pat<(v16i8 (MemLoad ADDRri:$addr)), (LV32BMainmem_U ADDRri:$addr)>;
def : Pat<(v16i8 (ScratchpadLoad ADDRri:$addr)), (LV32BScratchpad_U ADDRri:$addr)>;
def : Pat<(v16i16 (MemLoad ADDRri:$addr)), (LV32SMainmem_U ADDRri:$addr)>;
def : Pat<(v16i16 (ScratchpadLoad ADDRri:$addr)), (LV32SScratchpad_U ADDRri:$addr)>;
def : Pat<(v16i32 (ScratchpadLoad ADDRri:$addr)), (LV32WScratchpad_U ADDRri:$addr)>;

def : Pat<(MemStore v16i8:$dstsrc, ADDRri:$addr), (SV32BMainmem_U v16i8:$dstsrc, ADDRri:$addr)>;
def : Pat<(MemStore v16i16:$dstsrc, ADDRri:$addr), (SV32SMainmem_U v16i16:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16i8:$dstsrc, ADDRri:$addr), (SV32BScratchpad_U v16i8:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16i16:$dstsrc, ADDRri:$addr), (SV32SScratchpad_U v16i16:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16i32:$dstsrc, ADDRri:$addr), (SV32WScratchpad_U v16i32:$dstsrc, ADDRri:$addr)>;

def : Pat<(v16f32 (MemLoad ADDRri:$addr)), (LV32WMainmem_U ADDRri:$addr)>;
def : Pat<(v16f32 (ScratchpadLoad ADDRri:$addr)), (LV32WScratchpad_U ADDRri:$addr)>;

def : Pat<(MemStore v16f32:$dstsrc, ADDRri:$addr), (SV32WMainmem_U v16f32:$dstsrc, ADDRri:$addr)>;
def : Pat<(ScratchpadStore v16f32:$dstsrc, ADDRri:$addr), (SV32WScratchpad_U v16f32:$dstsrc, ADDRri:$addr)>;

// Questi pattern servono per gestire i tipi di dato vettoriali di dim < 512 bits
// v16i8 <=> v16i32
def : Pat<(v16i32 (bitconvert v16i8:$src)), (v16i32 (SEXT8_32VV_U v16i8:$src))>;
def : Pat<(MemStore (v16i8 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32BMainmem_U v16i32:$src, ADDRri:$addr)>;
def : Pat<(ScratchpadStore (v16i8 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32BScratchpad_U v16i32:$src, ADDRri:$addr)>;
// v16i16 <=> v16i32
def : Pat<(v16i32 (bitconvert v16i16:$src)), (v16i32 (SEXT16_32VV_U v16i16:$src))>;
def : Pat<(MemStore (v16i16 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32SMainmem_U v16i32:$src, ADDRri:$addr)>;
def : Pat<(ScratchpadStore (v16i16 (bitconvert v16i32:$src)), ADDRri:$addr), (SV32SScratchpad_U v16i32:$src, ADDRri:$addr)>;

// v8f32 <=> v16f32
//def : Pat<(MemStore (v8f32 (extract_subvector v16f32:$src, (i32 0))), ADDRri:$addr), (SV32WMainmem_U v16f32:$src, ADDRri:$addr)>;
//def : Pat<(ScratchpadStore (v8f32 (extract_subvector v16f32:$src, (i32 0))), ADDRri:$addr), (SV32WScratchpad_U v16f32:$src, ADDRri:$addr)>;

//---------------- Patterns for type conversions ----------------//

// Sign Extension Patterns sext_inreg -> sext
def : Pat<(v16i32 (sext_inreg v16i32:$src, v16i8)), (v16i32 (SEXT8_32VV_U v16i32:$src))>;
def : Pat<(v16i32 (sext_inreg v16i32:$src, v16i16)), (v16i32 (SEXT16_32VV_U v16i32:$src))>;

// BITCAST patterns
def : Pat<(f32 (bitconvert (i32 GPR32:$src))), (f32 GPR32:$src)>;
def : Pat<(i32 (bitconvert (f32 GPR32:$src))), (i32 GPR32:$src)>;
def : Pat<(v16f32 (bitconvert (v16i32 VR512W:$src))), (v16f32 VR512W:$src)>;
def : Pat<(v16i32 (bitconvert (v16f32 VR512W:$src))), (v16i32 VR512W:$src)>;

// CLZ and CTZ Intrinsics
def : Pat<(i32 (int_nuplus_clzi32 i32:$src)),
(i32 (CLZSS_32 i32:$src))>;
def : Pat<(v16i32 (int_nuplus_clzv16i32 v16i32:$src)),
(v16i32 (CLZVV_U_32 v16i32:$src))>;

def : Pat<(i32 (int_nuplus_ctzi32 i32:$src)),
(i32 (CTZSS_32 i32:$src))>;

def : Pat<(v16i32 (int_nuplus_ctzv16i32 v16i32:$src)),
(v16i32 (CTZVV_U_32 v16i32:$src))>;

// Integer division
// v16i32
def : Pat<(v16i32 (sdiv v16i32:$src1, v16i32:$src2)),
(F32TOI32_VV_U (DIVFVVV_U_32 (I32TOF32_VV_U v16i32:$src1), (I32TOF32_VV_U v16i32:$src2)))>;

// Branch patterns
def : Pat<(brcond (i32 (setne i32:$lhs, 0)), bb:$addr), (BNEZ i32:$lhs, bb:$addr)>;
def : Pat<(brcond (i32 (seteq i32:$lhs, 0)), bb:$addr), (BEQZ i32:$lhs, bb:$addr)>;
def : Pat<(brcond i32:$lhs, bb:$addr), (BNEZ i32:$lhs, bb:$addr)>;

// Call patterns
def : Pat<(call tglobaladdr:$addr), (JMPSR_OFF tglobaladdr:$addr)>;
def : Pat<(call texternalsym:$addr), (JMPSR_OFF texternalsym:$addr)>;

// GetLane patterns
def : Pat<(extractelt v16f32:$src0, i32:$src1),
(GET_LANEI_32 v16f32:$src0, i32:$src1)>;
def : Pat<(extractelt v16f32:$src, simm9:$imm),
(GET_LANEIimm v16f32:$src, imm:$imm)>;

// ISD Nodes Patterns
def : Pat<(i32 (leah tglobaladdr:$addr)), (LEAH tglobaladdr:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tglobaladdr:$addr)), (LEAL i32:$addrh, tglobaladdr:$addr)>;
def : Pat<(i32 (leah tconstpool:$addr)), (LEAH tconstpool:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tconstpool:$addr)), (LEAL i32:$addrh, tconstpool:$addr)>;
def : Pat<(i32 (leah tblockaddress:$addr)), (LEAH tblockaddress:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tblockaddress:$addr)), (LEAL i32:$addrh, tblockaddress:$addr)>;
def : Pat<(i32 (leah tjumptable:$addr)), (LEAH tjumptable:$addr)>;
def : Pat<(i32 (leal i32:$addrh, tjumptable:$addr)), (LEAL i32:$addrh, tjumptable:$addr)>;
</syntaxhighlight>

NuPlusInstrInfo.td

2019-06-21T15:01:52Z

Francesco: Francesco moved page NuPlusInstrInfo.td to NaplesPUInstrInfo.td

#REDIRECT [[NaplesPUInstrInfo.td]]

NaplesPUInstrFormats.td

2019-06-21T15:01:06Z

Francesco:

[[Category:Tablegen Files]]
The NaplesPUInstrFormats.td contains the classes that describe the [[ISA|NaplesPU instruction formats]], support classes to facilitate the instructions definition and also the definition nodes which make the pattern recognition easier.

<syntaxhighlight>
//===-- NaplesPUInstrFormats.td - NaplesPU Instruction Formats ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//

def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
def simm9 : PatLeaf<(imm), [{ return isInt<9>(N->getSExtValue()); }]>;

// Addressing modes as in SPARC
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
def V16ADDRri : ComplexPattern<v16i32, 2, "SelectADDRri", [], []>;
def V8ADDRri : ComplexPattern<v8i64, 2, "SelectADDRri", [], []>;

//===----------------------------------------------------------------------===//
// NaplesPU profiles and nodes
//===----------------------------------------------------------------------===//
// Transformation nodes
def LO32I : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getAPIntValue().getLoBits(32).getZExtValue(), SDLoc(N), MVT::i32);}]>;

def HI32I : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return CurDAG->getTargetConstant((unsigned)N->getAPIntValue().getHiBits(32).getZExtValue(), SDLoc(N), MVT::i32);}]>;

def LO32F : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant((unsigned)(N->getValueAPF().bitcastToAPInt().getLoBits(32).getZExtValue()), SDLoc(N), MVT::i32);}]>;

def HI32F : SDNodeXForm<fpimm, [{
// Transformation function: shift the immediate value down into the low bits.
return CurDAG->getTargetConstant((unsigned)(N->getValueAPF().bitcastToAPInt().getHiBits(32).getZExtValue()), SDLoc(N), MVT::i32);}]>;

def DIV2 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() / 2, SDLoc(N), MVT::i32);}]>;

// Moveil/moveih nodes definition, used for globaladdress lowering
def leah : SDNode<"NaplesPUISD::LEAH", SDTypeProfile<1, 1, []>>;
def leal : SDNode<"NaplesPUISD::LEAL", SDTypeProfile<1, 2, []>>;

// A splat is a vector with the same value in all lanes. Used to handle operation
// with both vector and scalar operands.
def splat : SDNode<"NaplesPUISD::SPLAT", SDTypeProfile<1, 1, [SDTCisEltOfVec<1, 0>]>>;

def return : SDNode<"NaplesPUISD::RET_FLAG", SDTypeProfile<0, 0, []>,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;

def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;

def call : SDNode<"NaplesPUISD::CALL", SDT_SPCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;

//To mark the beginning and end of a call sequence
def SDT_SPCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
def SDT_SPCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
[SDNPHasChain, SDNPSideEffect,
SDNPOptInGlue, SDNPOutGlue]>;
//To handle the lack of conditional moves
def selcondresult : SDNode<"NaplesPUISD::SEL_COND_RESULT", SDTypeProfile<1, 3,
[SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>>;

//===----------------------------------------------------------------------===//
// Operand Definitions
//===----------------------------------------------------------------------===//

// Used for the LEA_Sym, to detect the lea pseudo instruction
def symref : Operand<OtherVT> {}

def SIMM16OP : Operand<i32> {
let DecoderMethod = "decodeSimm16Value";
}

def SIMM9OP : Operand<i32> {
let DecoderMethod = "decodeSimm9Value";
}

def MemAsmOperand : AsmOperandClass {
let Name = "Mem";
let ParserMethod = "ParseMemoryOperand";
}

def MEMri : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeMemoryOpValue";
let DecoderMethod = "decodeScalarMemoryOpValue";
let ParserMatchClass = MemAsmOperand;
let MIOperandInfo = (ops GPR32, i32imm);
}

def V16MEMri : Operand<v16i32> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeMemoryOpValue";
let DecoderMethod = "decodeVectorWMemoryOpValue";
let ParserMatchClass = MemAsmOperand;
let MIOperandInfo = (ops VR512W, i32imm);
}

def LEAri : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeLEAValue";
let ParserMatchClass = MemAsmOperand; //TODO: controllare se è corretto il ParserMatchClass
let MIOperandInfo = (ops GPR32, i32imm);
}

def ABSh : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeABShValue";
let ParserMatchClass = MemAsmOperand; //TODO: controllare se è corretto il ParserMatchClass
let MIOperandInfo = (ops i32imm);
}

def ABSl : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeABSlValue";
let ParserMatchClass = MemAsmOperand; //TODO: controllare se è corretto il ParserMatchClass
let MIOperandInfo = (ops i32imm);
}

def brtarget : Operand<OtherVT>
{
let EncoderMethod = "encodeBranchTargetOpValue";
let DecoderMethod = "decodeBranchTargetOpValue";
}

def calltarget : Operand<iPTR>
{
let EncoderMethod = "encodeBranchTargetOpValue";
let DecoderMethod = "decodeBranchTargetOpValue";
}

//===----------------------------------------------------------------------===//
// Pattern fragments
//===----------------------------------------------------------------------===//
// Definition of anyextload used in the loading of vector types < 512 bits
def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr),
[{ return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;}]>;

//----------------------------------------------------------------------------//
//------------------------------ LOAD AND STORE ------------------------------//
//----------------------------------------------------------------------------//

def MemStore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return !cast<StoreSDNode>(N)->isTruncatingStore();
else
return false;}]>;

def MemLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
else
return false;}]>;

def ScratchpadStore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return !cast<StoreSDNode>(N)->isTruncatingStore();
else
return false;}]>;

def ScratchpadLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
else
return false;}]>;

//---------------- EXTLOAD scalar ----------------//
def extloadi1_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def extloadi1_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def extloadi8_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def extloadi8_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def extloadi16_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def extloadi16_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def extloadi32_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def extloadi32_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- ZEXTLOAD scalar ----------------//
def zextloadi1_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def zextloadi1_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def zextloadi8_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def zextloadi8_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def zextloadi16_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def zextloadi16_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def zextloadi32_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def zextloadi32_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- ZEXTLOAD vector ----------------//
def zextloadv16i8_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def zextloadv16i8_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def zextloadv16i16_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def zextloadv16i16_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def zextloadv8i8_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def zextloadv8i8_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def zextloadv8i16_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def zextloadv8i16_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def zextloadv8i32_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def zextloadv8i32_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

//---------------- SEXTLOAD scalar ----------------//
def sextloadi1_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def sextloadi1_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def sextloadi8_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def sextloadi8_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def sextloadi16_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def sextloadi16_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def sextloadi32_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def sextloadi32_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- SEXTLOAD vector ----------------//
def sextloadv16i8_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def sextloadv16i8_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def sextloadv16i16_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def sextloadv16i16_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def sextloadv8i8_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def sextloadv8i8_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def sextloadv8i16_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def sextloadv8i16_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def sextloadv8i32_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def sextloadv8i32_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

//---------------- ANYEXTLOAD vector ----------------//
def anyextloadv16i8_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def anyextloadv16i8_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def anyextloadv16i16_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def anyextloadv16i16_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def anyextloadv8i8_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def anyextloadv8i8_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def anyextloadv8i16_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def anyextloadv8i16_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def anyextloadv8i32_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def anyextloadv8i32_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

//---------------- TRUNCSTORE scalar ----------------//
def truncstorei1_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def truncstorei1_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def truncstorei8_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def truncstorei8_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def truncstorei16_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def truncstorei16_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def truncstorei32_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def truncstorei32_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- TRUNCSTORE vector ----------------//
def truncstorev16i8_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def truncstorev16i8_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def truncstorev16i16_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def truncstorev16i16_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def truncstorev8i8_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def truncstorev8i8_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def truncstorev8i16_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def truncstorev8i16_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def truncstorev8i32_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def truncstorev8i32_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

// insertelt SDNode redefinition
def VecInsert : SDTypeProfile<1, 3, [ // vector insert
SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
]>;

def insert_elt : SDNode<"ISD::INSERT_VECTOR_ELT", VecInsert>;

//===----------------------------------------------------------------------===//
// Describe NaplesPU Special Registers
//
//
//===----------------------------------------------------------------------===//

class SpReg<bits<6> reg> {
bits<6> Register = reg;
}

def MaskReg : SpReg<59>;

//===----------------------------------------------------------------------===//
// Describe NaplesPU scalar or vector instructions
//
// Fmt - 0 if a register is scalar, 1 if vector
//===----------------------------------------------------------------------===//

class Fmt<bit val> {
bit Value = val;
}

def Fmt_S : Fmt<0>;
def Fmt_V : Fmt<1>;

//===----------------------------------------------------------------------===//
// Describe NaplesPU instructions format here
//===----------------------------------------------------------------------===//

class InstNaplesPU<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
field bits<32> Inst;

let Namespace = "NaplesPU";
let Size = 4;

dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;

//let DecoderNamespace = "NaplesPU";
field bits<32> SoftFail = 0;
}

//===----------------------------------------------------------------------===//
// Format R instruction class in NaplesPU : <00|opcode|rd|rs0|rs1|unused|l|fmt|m|>
// l: if 1, 64 bit mode
// fmt2: FMT value for rd register
// fmt1: FMT value for rs0 register
// fmt0: FMT value for rs1 register
// m: if 1, masked
//
//===----------------------------------------------------------------------===//

class FR<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0, bit m>
: InstNaplesPU<outs, ins, asmstr, pattern> {
bits <6> dst;
bits <6> src0;

let Inst{31-30} = 0;
let Inst{29-24} = opcode;
let Inst{23-18} = dst;
let Inst{17-12} = src0;
let Inst{5} = 0; //unused
let Inst{4} = l;
let Inst{3} = fmt2.Value;
let Inst{2} = fmt1.Value;
let Inst{1} = fmt0.Value;
let Inst{0} = m;
}

class FR_TwoOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0, bit m>
: FR<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, m> {
bits <6> src1;

let Inst{11-6} = src1;
}

class FR_OneOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0, bit m>
: FR<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, m> {

let Inst{11-6} = 0;
}

class FR_TwoOp_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, 1> {
let Uses = [MR_REG];
}

class FR_TwoOp_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, 0> {

}

class FR_OneOp_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1>
: FR_OneOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, Fmt_S, 1> {
let Uses = [MR_REG];
}

class FR_OneOp_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1>
: FR_OneOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, Fmt_S, 0> {

}

class FR_TwoOp_Masked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Masked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1, fmt0> {

}

class FR_TwoOp_Masked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Masked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1, fmt0> {

}

class FR_TwoOp_Unmasked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Unmasked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1, fmt0> {

}

class FR_TwoOp_Unmasked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Unmasked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1, fmt0> {

}

class FR_OneOp_Masked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Masked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1> {

}

class FR_OneOp_Masked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Masked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1> {

}

class FR_OneOp_Unmasked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Unmasked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1> {

}

class FR_OneOp_Unmasked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Unmasked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1> {

}

//===----------------------------------------------------------------------===//
// Format I instruction class in NaplesPU : <010|opcode|rd|rs|imm|fmt|m|>
// fmt1: FMT value for rd register
// fmt0: FMT value for rs register
// m: if 1 masked
//===----------------------------------------------------------------------===//

class FI<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0, bit m>
: InstNaplesPU<outs, ins, asmstr, pattern> {
bits <6> dst;
bits <9> imm;

let Inst{31-29} = 0b010;
let Inst{28-24} = opcode;
let Inst{23-18} = dst;
let Inst{11-3} = imm;
let Inst{2} = fmt1.Value;
let Inst{1} = fmt0.Value;
let Inst{0} = m;
}

class FI_OneOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0, bit m> : FI<outs, ins, asmstr, pattern, opcode, fmt1, fmt0, m> {
bits <6> src;

let Inst{17-12} = src;
}

class FI_NoOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1> : FI<outs, ins, asmstr, pattern, opcode, fmt1, Fmt_S, 0> {
let Inst{17-12} = 0;
}

class FI_OneOp_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0> : FI_OneOp<outs, ins, asmstr, pattern, opcode, fmt1, fmt0, 1> {
let Uses = [MR_REG];
}

class FI_OneOp_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0> : FI_OneOp<outs, ins, asmstr, pattern, opcode, fmt1, fmt0, 0> {

}

//===----------------------------------------------------------------------===//
// Format MOVEI instruction class in NaplesPU : <01100|opcode|rd|imm|fmt|m|>
//===----------------------------------------------------------------------===//

class FMOVEI<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode, Fmt fmt, bit m>
: InstNaplesPU<outs, ins, asmstr, pattern> {
bits <6> dst;
bits <16> imm;

let Inst{31-27} = 0b01100;
let Inst{26-24} = opcode;
let Inst{23-18} = dst;
let Inst{17-2} = imm;
let Inst{1} = fmt.Value;
let Inst{0} = m;
}

//===----------------------------------------------------------------------===//
// Format M instruction class in NaplesPU : <10|opcode|rd/rs|rptr|off|l|s|m|>
//===----------------------------------------------------------------------===//

class FM<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, bit s, bit m>
: InstNaplesPU<outs, ins, asmstr, pattern> {
bits <6> dstsrc;
bits <15> addr; //base address and offset encoded on the same 15 bits value (check encodeMemoryOpValue)

let Inst{31-30} = 0b10;
let Inst{29-24} = opcode;
let Inst{23-18} = dstsrc;
let Inst{17-12} = addr{5-0};
let Inst{11-3} = addr{14-6};
let Inst{2} = l;
let Inst{1} = s;
let Inst{0} = m;
}

class FM_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, bit s>
: FM<outs, ins, asmstr, pattern, opcode, l, s, 0> {
}

class FM_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, bit s>
: FM<outs, ins, asmstr, pattern, opcode, l, s, 1> {
let Uses = [MR_REG];
}

class FM_Unmasked_Mainmem<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Unmasked<outs, ins, asmstr, pattern, opcode, l, 0> {
}

class FM_Unmasked_Scratchpad<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Unmasked<outs, ins, asmstr, pattern, opcode, l, 1> {
}

class FM_Masked_Mainmem<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Masked<outs, ins, asmstr, pattern, opcode, l, 0> {
}

class FM_Masked_Scratchpad<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Masked<outs, ins, asmstr, pattern, opcode, l, 1> {
}

class FM_Unmasked_Mainmem_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Mainmem<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Unmasked_Scratchpad_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Scratchpad<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Masked_Mainmem_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Mainmem<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Masked_Scratchpad_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Scratchpad<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Unmasked_Mainmem_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Mainmem<outs, ins, asmstr, pattern, opcode, 1> {
}

class FM_Unmasked_Scratchpad_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Scratchpad<outs, ins, asmstr, pattern, opcode, 1> {
}

class FM_Masked_Mainmem_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Mainmem<outs, ins, asmstr, pattern, opcode, 1> {
}

class FM_Masked_Scratchpad_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Scratchpad<outs, ins, asmstr, pattern, opcode, 1> {
}

//===----------------------------------------------------------------------===//
// Format J/BR instruction class in NaplesPU
// FJR: <0111|type(0/1)|opcode|rd|imm|>
// FJ: <0111|type(0/1)|opcode|imm|>
//===----------------------------------------------------------------------===//

class FJ_ALL<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: InstNaplesPU<outs, ins, asmstr, pattern> {

let Inst{31-28} = 0b0111;
let Inst{26-24} = opcode;
let isBranch = 1;
}

class FJR<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: FJ_ALL<outs, ins, asmstr, pattern, opcode> {
bits <6> cond;
bits <18> addr;

let Inst{27} = 0;
let Inst{23-18} = cond;
let Inst{17-0} = addr;
}

class FJ<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: FJ_ALL<outs, ins, asmstr, pattern, opcode> {
bits <24> addr;

let Inst{27} = 1;
let Inst{23-0} = addr;
}

//===----------------------------------------------------------------------===//
// Format C instruction class in NaplesPU
// FC: <01101|opcode|rs0|rs1|unused|>
//===----------------------------------------------------------------------===//

class FC<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: InstNaplesPU<outs, ins, asmstr, pattern> {

bits <6> src0;
bits <6> src1;

let Inst{31-27} = 0b01101;
let Inst{26-24} = opcode;
let Inst{23-18} = src0;
let Inst{17-12} = src1;
let Inst{11-0} = 0; //unused
}

//===----------------------------------------------------------------------===//
// A set of multiclasses is used to handle Vector/Scalar combinations
// SS: Scalar = Op Scalar
// VV: Vector = Op Vector
// SI: Vector = Op Immediate
// SSS: Scalar = Scalar Op Scalar
// VVS: Vector = Vector Op Scalar
// VVV: Vector = Vector Op Vector
// SVV: Scalar = Vector Op Vector
// SSI: Scalar = Vector Op Immediate
// VVI: Scalar = Vector Op Immediate
//===----------------------------------------------------------------------===//

multiclass FArithInt_TwoOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SSS - 32 bit integer
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (OpNode i32:$src0, i32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - VVS unmasked - 32 bit integer
def VVS_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV unmasked - 32 bit integer
def VVV_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, v16i32:$src1))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VVS masked - 32 bit integer
def VVS_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV masked - 32 bit integer
def VVV_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src0, v16i32:$src1),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

}
// FI - SSI
def SSI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins GPR32:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (OpNode i32:$src, (i32 simm9:$imm)))],
opcode{4-0},
Fmt_S,
Fmt_S>;

// FI - VVI unmasked
def VVI_U : FI_OneOp_Unmasked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set v16i32:$dst, (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))))],
opcode{4-0},
Fmt_V,
Fmt_V>;

// FI - VVI masked
let Constraints = "$dst = $oldvalue" in {
def VVI_M : FI_OneOp_Masked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm, VR512W:$oldvalue),
operator # "i.m $dst, $src, $imm",
[(set v16i32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))), v16i32:$oldvalue))],
opcode{4-0},
Fmt_V,
Fmt_V>;
}
}

multiclass FArithInt_OneOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SS - 32 bit integer
def SS_32 : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
operator # "_i32 $dst, $src0",
[(set i32:$dst, (OpNode i32:$src0))],
opcode,
Fmt_S,
Fmt_S>;

// FR - VV unmasked - 32 bit integer
def VV_U_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
operator # "_i32 $dst, $src0",
[(set v16i32:$dst, (OpNode v16i32:$src0))],
opcode,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VV masked - 32 bit integer
def VV_M_32 : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0",
[(set v16i32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src0),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V>;

}
}

// per la shift rotate
multiclass FSRInt_TwoOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SSS - 32 bit integer
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (OpNode i32:$src0, i32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - VVS unmasked - 32 bit integer
def VVS_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV unmasked - 32 bit integer
def VVV_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, v16i32:$src1))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VVS masked - 32 bit integer
def VVS_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV masked - 32 bit integer
def VVV_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src0, v16i32:$src1),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

}
// FI - SSI
def SSI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins GPR32:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (OpNode i32:$src, (i32 simm9:$imm)))],
opcode{4-0},
Fmt_S,
Fmt_S>;

// FI - VVI unmasked
def VVI_U : FI_OneOp_Unmasked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set v16i32:$dst, (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))))],
opcode{4-0},
Fmt_V,
Fmt_V>;

// FI - VVI masked
let Constraints = "$dst = $oldvalue" in {
def VVI_M : FI_OneOp_Masked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm, VR512W:$oldvalue),
operator # "i.m $dst, $src, $imm",
[(set v16i32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))), v16i32:$oldvalue))],
opcode{4-0},
Fmt_V,
Fmt_V>;
}
}

multiclass FArithFloat_TwoOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SSS - 32 bit float
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set f32:$dst, (OpNode f32:$src0, f32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - VVS unmasked - 32 bit float
def VVS_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set v16f32:$dst, (OpNode v16f32:$src0, (splat f32:$src1)))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV unmasked - 32 bit float
def VVV_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set v16f32:$dst, (OpNode v16f32:$src0, v16f32:$src1))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VVS masked - 32 bit float
def VVS_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1, VR512W:$oldvalue),
operator # "_f32.m $dst, $src0, $src1",
[(set v16f32:$dst, (int_npu_vector_mixf32 (OpNode v16f32:$src0, (splat f32:$src1)),
v16f32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV masked - 32 bit float
def VVV_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1, VR512W:$oldvalue),
operator # "_f32.m $dst, $src0, $src1",
[(set v16f32:$dst, (int_npu_vector_mixf32 (OpNode v16f32:$src0, v16f32:$src1),
v16f32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;
}
}

multiclass FArithFloat_OneOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SS - 32 bit float
def SS_32 : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
operator # "_f32 $dst, $src0",
[(set f32:$dst, (OpNode f32:$src0))],
opcode,
Fmt_S,
Fmt_S>;

// FR - VV unmasked - 32 bit float
def VV_U_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
operator # "_f32 $dst, $src0",
[(set v16f32:$dst, (OpNode v16f32:$src0))],
opcode,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VV masked - 32 bit float
def VV_M_32 : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
operator # "_f32.m $dst, $src0",
[(set v16f32:$dst, (int_npu_vector_mixi32 (OpNode v16i32:$src0),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V>;
}
}

// Condition codes defined in include/llvm/CodeGen/ISDOpcodes.h
// VS and VV comparisons are handled through intrinsics
multiclass FCompInt<string operator, CondCode condition,
bits<6> opcode, Intrinsic vectorIntr32> {
// FR - SSS - 32 bit integer
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (setcc i32:$src0, i32:$src1, condition))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - SVS unmasked - 32 bit integer
def SVS_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16i32:$src0, (splat i32:$src1)))],
opcode,
Fmt_S,
Fmt_V,
Fmt_S>;

// FR - SVV unmasked - 32 bit integer
def SVV_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16i32:$src0, v16i32:$src1))],
opcode,
Fmt_S,
Fmt_V,
Fmt_V>;

// FI - SSI
def SSI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins GPR32:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (setcc i32:$src, simm9:$imm, condition))],
opcode{4-0},
Fmt_S,
Fmt_S>;

// FI - SVI unmasked
def SVI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (vectorIntr32 v16i32:$src, (splat simm9:$imm)))],
opcode{4-0},
Fmt_S,
Fmt_V>;
}

multiclass FCompFloat<string operator, SDNode OpNode,
bits<6> opcode, Intrinsic vectorIntr32> {
// FR - SSS - 32 bit float
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set i32:$dst, (OpNode f32:$src0, f32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - SVS unmasked - 32 bit float
def SVS_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16f32:$src0, (splat f32:$src1)))],
opcode,
Fmt_S,
Fmt_V,
Fmt_S>;

// FR - SVV unmasked - 32 bit float
def SVV_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16f32:$src0, v16f32:$src1))],
opcode,
Fmt_S,
Fmt_V,
Fmt_V>;

}

multiclass FSext_32<string operator, ValueType vt,
bits<6> opcode, ValueType vt_v> {
// FR - SS
def SS : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
operator # "_i32 $dst, $src0",
[(set i32:$dst, (sext_inreg i32:$src0, vt))],
opcode,
Fmt_S,
Fmt_S>;

// FR - VV unmasked
def VV_U : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
operator # "_i32 $dst, $src0",
[(set v16i32:$dst, (sext vt_v:$src0))],
opcode,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VV masked
def VV_M : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0",
[(set v16i32:$dst, (int_npu_vector_mixi32 (sext vt_v:$src0),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V>;
}
}

//===----------------------------------------------------------------------===//
// A set of multiclasses used to handle Loads and Stores
//===----------------------------------------------------------------------===//

// Scalar LOAD
multiclass FMLoadScalar_32<string suffix, PatFrag op_mem, PatFrag op_scratch, bits<6> opcode> {

def _Mainmem : FM_Unmasked_Mainmem<
(outs GPR32:$dstsrc),
(ins MEMri:$addr),
"load32" # suffix # " $dstsrc, $addr",
[(set i32:$dstsrc, (i32 (op_mem ADDRri:$addr)))],
opcode,
0>;

def _Scratchpad : FM_Unmasked_Scratchpad<
(outs GPR32:$dstsrc),
(ins MEMri:$addr),
"load32" # suffix # "_scratchpad $dstsrc, $addr",
[(set i32:$dstsrc, (i32 (op_scratch ADDRri:$addr)))],
opcode,
0>;

}

// Scalar STORE
multiclass FMStoreScalar_32<string suffix, PatFrag op_mem, PatFrag op_scratch, bits<6> opcode> {

def _Mainmem : FM_Unmasked_Mainmem<
(outs),
(ins GPR32:$dstsrc, MEMri:$addr),
"store32" # suffix # " $dstsrc, $addr",
[(op_mem i32:$dstsrc, ADDRri:$addr)],
opcode,
0>;

def _Scratchpad : FM_Unmasked_Scratchpad<
(outs),
(ins GPR32:$dstsrc, MEMri:$addr),
"store32" # suffix # "_scratchpad $dstsrc, $addr",
[(op_scratch i32:$dstsrc, ADDRri:$addr)],
opcode,
0>{
let hasSideEffects = 1;
let mayStore = 1;
}
}

// Vector LOAD
multiclass FMLoadVector_32<string suffix, PatFrag op_Umem, PatFrag op_Uscratch,
Intrinsic op_Mmem, Intrinsic op_Mscratch, bits<6> opcode> {

// main memory - unmasked - 32
def Mainmem_U : FM_Unmasked_Mainmem_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # " $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Umem ADDRri:$addr))],
opcode>;

// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # "_scratchpad $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Uscratch ADDRri:$addr))],
opcode>;

// main memory - masked - 32
def Mainmem_M : FM_Masked_Mainmem_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # ".m $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Mmem ADDRri:$addr))],
opcode>;

// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # "_scratchpad.m $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Mscratch ADDRri:$addr))],
opcode>;
}

// Vector GATHER
multiclass FMGather_32<string suffix, Intrinsic op_Uscratch,
Intrinsic op_Mscratch, bits<6> opcode> {

// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins V16MEMri:$addr),
"loadg" # suffix # "_scratchpad $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Uscratch V16ADDRri:$addr))],
opcode>;
// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins V16MEMri:$addr),
"loadg" # suffix # "_scratchpad.m $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Mscratch V16ADDRri:$addr))],
opcode>;
}

// Vector STORE
multiclass FMStoreVector_32<string suffix, PatFrag op_Umem, PatFrag op_Uscratch,
Intrinsic op_Mmem, Intrinsic op_Mscratch, bits<6> opcode> {

// main memory - unmasked - 32
def Mainmem_U : FM_Unmasked_Mainmem_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # " $dstsrc, $addr",
[(op_Umem v16i32:$dstsrc, ADDRri:$addr)],
opcode>;
// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # "_scratchpad $dstsrc, $addr",
[(op_Uscratch v16i32:$dstsrc, ADDRri:$addr)],
opcode>;
// main memory - masked - 32
def Mainmem_M : FM_Masked_Mainmem_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # ".m $dstsrc, $addr",
[(op_Mmem ADDRri:$addr, v16i32:$dstsrc)],
opcode>;
// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # "_scratchpad.m $dstsrc, $addr",
[(op_Mscratch ADDRri:$addr, v16i32:$dstsrc)],
opcode>;
}

// Vector SCATTER
multiclass FMScatter_32<string suffix, Intrinsic op_Uscratch,
Intrinsic op_Mscratch, bits<6> opcode> {

// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, V16MEMri:$addr),
"stores" # suffix # "_scratchpad $dstsrc, $addr",
[(op_Uscratch V16ADDRri:$addr, v16i32:$dstsrc)],
opcode>;

// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, V16MEMri:$addr),
"stores" # suffix # "_scratchpad.m $dstsrc, $addr",
[(op_Mscratch V16ADDRri:$addr, v16i32:$dstsrc)],
opcode>;
}

//===----------------------------------------------------------------------===//
// A set of multiclasses is used to handle Vector/Scalar
// Masked/Unmasked combinations
// MOVEI operations
//===----------------------------------------------------------------------===//

multiclass FMOVEI_ALL<string operator, bits<3> opcode> {
// SI
def SI : FMOVEI<
(outs GPR32:$dst),
(ins SIMM16OP:$imm),
operator # " $dst, $imm",
[],//[(set i32:$dst, simm16:$imm)],
opcode,
Fmt_S,
0>;

// VI unmasked
def VI_U : FMOVEI<
(outs VR512W:$dst),
(ins SIMM16OP:$imm),
operator # " $dst, $imm",
[],//[(set v16i32:$dst, (splat simm16:$imm))],
opcode,
Fmt_V,
0>;

let Constraints = "$dst = $oldvalue", Uses = [MR_REG] in {
// VI masked
def VI_M : FMOVEI<
(outs VR512W:$dst),
(ins SIMM16OP:$imm, VR512W:$oldvalue),
operator # ".m $dst, $imm",
[(set v16i32:$dst, (int_npu_vector_mixi32 (splat simm16:$imm), v16i32:$oldvalue))],
opcode,
Fmt_V,
1>;
}
}

//===----------------------------------------------------------------------===//
// Instruction class used to read/write special register through intrinics
// All these instructions are implemented using a move instruction
//===----------------------------------------------------------------------===//
let DecoderNamespace = "Read_SPR" in {
class READ_SPR<SpReg reg, string operator, Intrinsic read_intr> :
FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins),
operator # " $dst",
[(set i32:$dst, (read_intr))],
32,
Fmt_S,
Fmt_S>
{
bits<6> dst;

let Inst{29-24} = 32; // opcode: move
let Inst{23-18} = dst;
let Inst{17-12} = reg.Register;
let Inst{11-6} = 0;
}
}
let DecoderNamespace = "Write_SPR" in {
class WRITE_SPR<SpReg reg, string operator, Intrinsic read_intr> :
FR_OneOp_Unmasked_32<
(outs),
(ins GPR32:$src),
operator # " $src",
[(read_intr i32:$src)],
32,
Fmt_S,
Fmt_S>
{
bits<6> src;

let Inst{29-24} = 32; // opcode: move
let Inst{23-18} = reg.Register;
let Inst{17-12} = src;
let Inst{11-6} = 0;
}
}

//===----------------------------------------------------------------------===//
// Pseudo-instructions for alternate assembly syntax (never used by codegen).
// These are aliases that require C++ handling to convert to the target
// instruction, while InstAliases can be handled directly by tblgen.
//===----------------------------------------------------------------------===//
class AsmPseudoInst<dag outs, dag ins, string asm>
: InstNaplesPU<outs, ins, asm, []> {
let isPseudo = 1;
}

class Pseudo<dag outs, dag ins, list<dag> pattern>
: InstNaplesPU<outs, ins, "Pseudo", pattern>
{
let isCodeGenOnly = 1;
let isPseudo = 1;
let Inst{31-0} = 0;
}

multiclass AtomicBinary<SDNode OpNode>
{
def R : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, GPR32:$amt),
[(set i32:$dst, (OpNode GPR32:$ptr, GPR32:$amt))]>;

def I : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, SIMM9OP:$amt),
[(set i32:$dst, (OpNode GPR32:$ptr, simm9:$amt))]>;
}

</syntaxhighlight>

NaplesPUISelDAGToDAG.cpp

2019-06-21T14:59:54Z

Francesco:

The NaplesPUDAGToDAGISel class is used to transform target independent LLVM DAG nodes into platform dependent nodes.

<syntaxhighlight>
//===-- NaplesPUISelDAGToDAG.cpp - A dag to dag inst selector for NaplesPU ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This pass transforms target independent LLVM DAG nodes into platform
// dependent nodes that map, for the most part, directly to target instructions.
//
//===----------------------------------------------------------------------===//

#define DEBUG_TYPE "naplespu-isel"

#include "NaplesPUTargetMachine.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;

namespace {
class NaplesPUDAGToDAGISel : public SelectionDAGISel {
public:
explicit NaplesPUDAGToDAGISel(NaplesPUTargetMachine &tm) : SelectionDAGISel(tm) {}

void Select(SDNode *N) override;

bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
std::vector<SDValue> &OutOps) override;

bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);

StringRef getPassName() const override {
return "NaplesPU DAG->DAG Pattern Instruction Selection";
}

#include "NaplesPUGenDAGISel.inc"
};
} // end anonymous namespace

bool NaplesPUDAGToDAGISel::SelectADDRri(SDValue Addr, SDValue &Base,
SDValue &Offset) {

if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
return true;
}

if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls.

if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
if (isInt<9>(CN->getSExtValue())) {
if (FrameIndexSDNode *FIN =
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
} else {
Base = Addr.getOperand(0);
}
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
MVT::i32);
return true;
}
}
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
return true;
}

void NaplesPUDAGToDAGISel::Select(SDNode *N) {
SDLoc DL(N);
if (N->isMachineOpcode())
return; // Already selected.

SelectCode(N);
}

bool NaplesPUDAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default:
return true;

case 'm': // memory
SelectADDRri(Op, Op0, Op1);
break;

}

OutOps.push_back(Op0);
OutOps.push_back(Op1);
return false;
}

FunctionPass *llvm::createNaplesPUISelDag(NaplesPUTargetMachine &TM) {
return new NaplesPUDAGToDAGISel(TM);
}
</syntaxhighlight>

NaplesPUCallingConv.td

2019-06-21T14:58:39Z

Francesco:

[[Category:Tablegen Files]]
This file describes the conventions to use when a function is called, such as how to pass the arguments and how to return the function results.

<syntaxhighlight>
//===-- NaplesPUCallingConv.td - Calling Conventions NaplesPU ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This describes the calling conventions for the NaplesPU architectures.
//
//===----------------------------------------------------------------------===//

def CC_NaplesPU32 : CallingConv<[

// i1, i8 and i16 integers are promoted to i32 by the caller.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,

CCIfType<[v16i8, v16i16], CCPromoteToType<v16i32>>,
CCIfType<[v8i8, v8i16, v8i32], CCPromoteToType<v8i64>>,

// i32 f32 arguments get passed in integer registers if there is space.
CCIfNotVarArg<CCIfType<[i32, f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>>,

// Vector arguments can be passed in their own registers, as above
CCIfNotVarArg<CCIfType<[v16i32, v16f32], CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>>,

// Stick remaining registers onto stack, aligned by size
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
CCIfType<[v16i32, v16f32], CCAssignToStack<64, 64>>
]>;

def RetCC_NaplesPU32 : CallingConv<[
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,

CCIfType<[i32, f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5]>>,

CCIfType<[v16i8, v16i16], CCPromoteToType<v16i32>>,

CCIfType<[v16i32, v16f32], CCAssignToReg<[V0, V1, V2, V3, V4, V5]>>
]>;

//Callee only needs to save the callee-save registers that are used in the body of its subroutine.
def NaplesPUCSR : CalleeSavedRegs<(add (sequence "S%u", 50, 57), MR_REG, FP_REG, RA_REG,
(sequence "V%u", 56, 63))>;
</syntaxhighlight>

NaplesPURegisterInfo.td

2019-06-21T14:56:45Z

Francesco:

[[Category:Tablegen Files]]
The NaplesPURegisterInfo.td is used to define the NaplesPU hw registers and the NaplesPU register classes.

<syntaxhighlight lang="c" line='line'>
//===-- NaplesPURegisterInfo.td - NaplesPU Register defs ---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Declarations that describe the NaplesPU register file
//===----------------------------------------------------------------------===//

let Namespace = "NaplesPU" in {
def sub_even : SubRegIndex<32>;
def sub_odd : SubRegIndex<32, 32>;
}

class NaplesPUReg<bits<16> Enc, string n> : Register<n> {
let HWEncoding = Enc;
let Namespace = "NaplesPU";
}

class NaplesPURegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
: RegisterWithSubRegs<n, subregs> {
let HWEncoding = Enc;
let Namespace = "NaplesPU";
}

// NaplesPU 32-bit registers
class NaplesPUGPRReg<bits<16> Enc, string n> : NaplesPUReg<Enc, n>;

//===----------------------------------------------------------------------===//
// Registers
//===----------------------------------------------------------------------===//

// General Purpose scalar registers
foreach i = 0-57 in {
def S#i : NaplesPUGPRReg<i, "s"#i>, DwarfRegNum<[i]>;
}

//trap register
def TR_REG : NaplesPUGPRReg<58, "tr">, DwarfRegNum<[58]>;
//mask register
def MR_REG : NaplesPUGPRReg<59, "rm">, DwarfRegNum<[59]>;
//frame pointer
def FP_REG : NaplesPUGPRReg<60, "fp">, DwarfRegNum<[60]>;
//stack pointer
def SP_REG : NaplesPUGPRReg<61, "sp">, DwarfRegNum<[61]>;
//return address
def RA_REG : NaplesPUGPRReg<62, "ra">, DwarfRegNum<[62]>;
//PC
def PC_REG : NaplesPUGPRReg<63, "pc">, DwarfRegNum<[63]>;

// General Purpose vectorial registers
foreach i = 0-63 in {
def V#i : NaplesPUGPRReg<i, "v"#i>, DwarfRegNum<[!add(i, 64)]>;
}

//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//

// This register class should not be used to hold i64/f64 values, use the GPR64
// register class for that. The i64/f64 type is included here to allow i64/f64
// patterns using the instructions.
def GPR32 : RegisterClass<"NaplesPU", [i32, f32], 32, (add (sequence "S%u", 0, 57),
TR_REG, MR_REG, FP_REG, SP_REG, RA_REG, PC_REG)>

def VR512W : RegisterClass<"NaplesPU", [v16i32, v16f32, v16i8, v16i16], 512, (sequence "V%u", 0, 63)>;
</syntaxhighlight>

NaplesPU.td

2019-06-21T14:55:37Z

Francesco:

[[Category:Tablegen Files]]
The NaplesPU.td file contains the definition of the Target class '''NaplesPU''' (defined in "compiler/include/llvm/Target/Target.td"). The file also contains the definition of the '''NaplesPUInstrInfo''', '''NaplesPUAsmParser''' and '''NaplesPUAsmWriter''' required by the '''Target''' class. In addition, we avoid using instruction itineraries for scheduling. Itineraries are details reservation tables for each instruction class.

<syntaxhighlight lang="c" line='line'>
//===-- NaplesPU.td - Describe the NaplesPU Target Machine -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//MCCodeEmitter/===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//

include "NaplesPURegisterInfo.td"
include "NaplesPUCallingConv.td"
include "NaplesPUInstrInfo.td"

def NaplesPUInstrInfo : InstrInfo;

def NaplesPUAsmParser : AsmParser {
bit ShouldEmitMatchRegisterName = 1;
}

//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//

def NaplesPUAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
bit isMCAsmWriter = 1;
}

def : Processor<"naplespu", NoItineraries, []>;

def NaplesPU : Target {
// Pull in Instruction Info:
let InstructionSet = NaplesPUInstrInfo;
let AssemblyParsers = [NaplesPUAsmParser];
let AssemblyWriters = [NaplesPUAsmWriter];
}

</syntaxhighlight>

NaplesPUMCCodeEmitter.cpp

2019-06-21T14:51:21Z

Francesco: Francesco moved page NuPlusMCCodeEmitter.cpp to NaplesPUMCCodeEmitter.cpp

NuPlusMCCodeEmitter class transforms MCInst objects into binary code representation.

<syntaxhighlight>
//===-- NuPlusMCCodeEmitter.cpp - Convert NuPlus code to machine code -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the NuPlusMCCodeEmitter class.
//
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/NuPlusFixupKinds.h"
#include "MCTargetDesc/NuPlusMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

using namespace llvm;

#define DEBUG_TYPE "mccodeemitter"

STATISTIC(MCNumEmitted, "Number of MC instructions emitted");

namespace {
class NuPlusMCCodeEmitter : public MCCodeEmitter {
NuPlusMCCodeEmitter(const NuPlusMCCodeEmitter &) = delete;
void operator=(const NuPlusMCCodeEmitter &) = delete;
MCContext &Ctx;

public:
NuPlusMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx): Ctx(ctx) {}

// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;

unsigned encodeMemoryOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeLEAValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeABShValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeABSlValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned encodeBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

// Emit one byte through output stream (from MCBlazeMCCodeEmitter)
void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; }

void EmitLEConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
assert(Size <= 8 && "size too big in emit constant");

for (unsigned i = 0; i != Size; ++i) {
EmitByte(Val & 255, OS);
Val >>= 8;
}
}

};
} // end anonymous namespace

MCCodeEmitter *llvm::createNuPlusMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx) {
return new NuPlusMCCodeEmitter(MCII, Ctx);
}

// Return binary encoding of operand.
unsigned NuPlusMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {

if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());

if (MO.isImm())
return static_cast<unsigned>(MO.getImm());

return 0;
}

void NuPlusMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
EmitLEConstant(Bits, 4, OS);

++MCNumEmitted; // Keep track of the # of mi's emitted.
}

unsigned NuPlusMCCodeEmitter::encodeABShValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// with LEAH the second operand is expected to be the global address
//MCOperand address = MI.getOperand(1);
// the third operand is the label used in the asm
//MCOperand address_asm = MI.getOperand(2);

if (MI.getOperand(1).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(1).getExpr(),
MCFixupKind(NuPlus::fixup_NuPlus_Absh)));
} else if ( MI.getOperand(2).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(2).getExpr(),
MCFixupKind(NuPlus::fixup_NuPlus_Absh)));
}

return 0;
}

unsigned NuPlusMCCodeEmitter::encodeABSlValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// with LEAH the third operand is expected to be the global address
//MCOperand address = MI.getOperand(2);
// the fourth operand is the label used in the asm
//MCOperand address_asm = MI.getOperand(3);

if (MI.getOperand(2).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(2).getExpr(),
MCFixupKind(NuPlus::fixup_NuPlus_Absl)));
} else if (MI.getOperand(3).isExpr()) {
Fixups.push_back(MCFixup::create(
0, MI.getOperand(3).getExpr(),
MCFixupKind(NuPlus::fixup_NuPlus_Absl)));
}

return 0;
}

unsigned NuPlusMCCodeEmitter::encodeLEAValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
MCOperand baseReg = MI.getOperand(1);
MCOperand offsetOp = MI.getOperand(2);

assert(baseReg.isReg() && "First operand of LEA op is not register.");
unsigned encoding = Ctx.getRegisterInfo()->getEncodingValue(baseReg.getReg())<<10;
if (offsetOp.isExpr()) {
// Load with a label. This is a PC relative load. Add a fixup.
Fixups.push_back(MCFixup::create(
0, offsetOp.getExpr(),
MCFixupKind(NuPlus::fixup_NuPlus_PCRel_Lea)));
} else if (offsetOp.isImm())
encoding |= static_cast<short>(offsetOp.getImm())<<1;
else
assert(offsetOp.isImm() && "Second operand of LEA op is unknown type.");

return encoding;
}

// Encode NuPlus Memory Operand. The result is a packed field with the
// register in the low 5 bits and the offset in the remainder. The instruction
// patterns will put these into the proper part of the instruction
// (NuPlusInstrFormats.td).
unsigned
NuPlusMCCodeEmitter::encodeMemoryOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned encoding;

MCOperand baseReg;
MCOperand offsetOp;

baseReg = MI.getOperand(1);
offsetOp = MI.getOperand(2);

// Register
// This is register/offset. No need for relocation.
assert(baseReg.isReg() && "First operand is not register.");
//encoding just the register
encoding = Ctx.getRegisterInfo()->getEncodingValue(baseReg.getReg());
// Offset
if (offsetOp.isExpr()) {
// Load with a label. This is a PC relative load. Add a fixup.
// XXX Note that this assumes unmasked instructions. A masked
// instruction will not work and should not be used. Check for this
// and return an error.
Fixups.push_back(
MCFixup::create(0, offsetOp.getExpr(),
MCFixupKind(NuPlus::fixup_NuPlus_PCRel_Mem)));
} else if (offsetOp.isImm())
encoding |= static_cast<short>(offsetOp.getImm()) << 6;
else
assert(offsetOp.isImm() && "Second operand of memory op is unknown type.");
return encoding;
}

// encodeBranchTargetOpValue - Return binary encoding of the jump
// target operand. If the machine operand requires relocation,
// record the relocation and return zero.
unsigned NuPlusMCCodeEmitter::encodeBranchTargetOpValue(
const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {

const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isImm())
return MO.getImm();

assert(MO.isExpr() &&
"encodeBranchTargetOpValue expects only expressions or an immediate");

const MCExpr *Expr = MO.getExpr();
Fixups.push_back(
MCFixup::create(0, Expr, MCFixupKind(NuPlus::fixup_NuPlus_Branch)));
return 0;
}

#include "NuPlusGenMCCodeEmitter.inc"

</syntaxhighlight>

NuPlusMCCodeEmitter.cpp

2019-06-21T14:51:21Z

Francesco: Francesco moved page NuPlusMCCodeEmitter.cpp to NaplesPUMCCodeEmitter.cpp

#REDIRECT [[NaplesPUMCCodeEmitter.cpp]]

NaplesPUInstPrinter.cpp

2019-06-21T14:49:34Z

Francesco: Francesco moved page NuPlusInstPrinter.cpp to NaplesPUInstPrinter.cpp

NuPlusInstPrinter.cpp

2019-06-21T14:49:34Z

Francesco: Francesco moved page NuPlusInstPrinter.cpp to NaplesPUInstPrinter.cpp

#REDIRECT [[NaplesPUInstPrinter.cpp]]

NaplesPUMCInstLower.cpp

2019-06-21T14:49:12Z

Francesco: Francesco moved page NuPlusMCInstLower.cpp to NaplesPUMCInstLower.cpp

The NuPlusMCInstLower class transforms the MachineInstr object into a simplified version, the MCInst one.

<syntaxhighlight>
//===-- NuPlusMCInstLower.cpp - Convert NuPlus MachineInstr to MCInst -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains code to lower NuPlus MachineInstrs to their corresponding
// MCInst records.
//
//===----------------------------------------------------------------------===//

#include "NuPlusAsmPrinter.h"
#include "NuPlusInstrInfo.h"
#include "NuPlusMCInstLower.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Debug.h"

#define GET_REGINFO_ENUM
#include "NuPlusGenRegisterInfo.inc"

using namespace llvm;

NuPlusMCInstLower::NuPlusMCInstLower(NuPlusAsmPrinter &asmprinter)
: AsmPrinter(asmprinter) {}

void NuPlusMCInstLower::Initialize(MCContext *C) {
Ctx = C;
}

//Derived from MipsMCInstLower
MCOperand NuPlusMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
MachineOperandType MOTy,
unsigned Offset) const {
MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
const MCSymbol *Symbol;

switch (MOTy) {
case MachineOperand::MO_MachineBasicBlock:
Symbol = MO.getMBB()->getSymbol();
break;

case MachineOperand::MO_GlobalAddress:
Symbol = AsmPrinter.getSymbol(MO.getGlobal());
Offset += MO.getOffset();
break;

case MachineOperand::MO_BlockAddress:
Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
Offset += MO.getOffset();
break;

case MachineOperand::MO_ExternalSymbol:
Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
Offset += MO.getOffset();
break;
case MachineOperand::MO_JumpTableIndex:
Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
break;
case MachineOperand::MO_ConstantPoolIndex:
Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
Offset += MO.getOffset();
break;

default:
llvm_unreachable("<unknown operand type>");
}

//TODO: controllare differenze con MIPS e come mai nel case manca MO_MCSymbol (anche nella funzione successiva)
const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Symbol, Kind, *Ctx);
if (!Offset)
return MCOperand::createExpr(MCSym);

// Assume offset is never negative.
assert(Offset > 0);
const MCConstantExpr *OffsetExpr = MCConstantExpr::create(Offset, *Ctx);
const MCBinaryExpr *Add = MCBinaryExpr::createAdd(MCSym, OffsetExpr, *Ctx);
return MCOperand::createExpr(Add);
}

MCOperand NuPlusMCInstLower::LowerOperand(const MachineOperand &MO,
unsigned offset) const {
MachineOperandType MOTy = MO.getType();

switch (MOTy) {
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) break;
return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
return MCOperand::createImm(MO.getImm() + offset);
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_BlockAddress:
return LowerSymbolOperand(MO, MOTy, offset);
case MachineOperand::MO_RegisterMask:
break;
}

return MCOperand();
}

void NuPlusMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());

// XXX note that this chunk of code assumes a load instruction. It's also
// possible for MO_ConstantPoolIndex to appear in arithmetic. In this
// situation, the instruction would be clobbered.
//TODO: questo if usato nel caso in cui l'istruzione usa costantpool o jumptable.
// noi non abbiamo la jump table. E la costant pool?? controllare e modificare
if (MI->getNumOperands() > 1 &&
(MI->getOperand(1).getType() == MachineOperand::MO_ConstantPoolIndex ||
MI->getOperand(1).getType() == MachineOperand::MO_JumpTableIndex)) {
OutMI.addOperand(LowerOperand(MI->getOperand(0))); // result

const MachineOperand &cpEntry = MI->getOperand(1);

// This is a PC relative constant pool access. Add the PC register
// to this instruction to match what the assembly parser produces
// (and InstPrinter/Encoder expects)
// It should look like this:
// <MCInst #97 LWi <MCOperand Reg:8> <MCOperand Reg:3> <MCOperand
// Expr:(foo)>>
OutMI.addOperand(MCOperand::createReg(NuPlus::PC_REG));
const MCSymbol *Symbol;
if (MI->getOperand(1).getType() == MachineOperand::MO_ConstantPoolIndex)
Symbol = AsmPrinter.GetCPISymbol(cpEntry.getIndex());
else
Symbol = AsmPrinter.GetJTISymbol(cpEntry.getIndex());

const MCSymbolRefExpr *MCSym =
MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, *Ctx);
MCOperand MCOp = MCOperand::createExpr(MCSym);
OutMI.addOperand(MCOp);
} else {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp = LowerOperand(MO);

if (MCOp.isValid())
OutMI.addOperand(MCOp);
}
}
}
</syntaxhighlight>

NuPlusMCInstLower.cpp

2019-06-21T14:49:12Z

Francesco: Francesco moved page NuPlusMCInstLower.cpp to NaplesPUMCInstLower.cpp

#REDIRECT [[NaplesPUMCInstLower.cpp]]

NaplesPUFrameLowering.cpp

2019-06-21T14:48:45Z

Francesco: Francesco moved page NuPlusFrameLowering.cpp to NaplesPUFrameLowering.cpp

[[Category:C++ Classes]]
The NuPlusFrameLowering class must handle all the operations concerning the stack frame. It implements the '''TargetFrameLowering''' interface.
In nu+ the stack grows incrementing the address (i.e. the stack grows down) and it is 64-byte aligned.

<syntaxhighlight>
//===-- NuPlusFrameLowering.cpp - NuPlus Frame Information -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the NuPlus implementation of TargetFrameLowering
// class.
//
//===----------------------------------------------------------------------===//

#include "NuPlusFrameLowering.h"
#include "MCTargetDesc/NuPlusMCTargetDesc.h"
#include "NuPlusInstrInfo.h"
#include "NuPlusMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetOptions.h"

using namespace llvm;

void NuPlusFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
assert(&MF.front() == &MBB);
MachineFrameInfo &MFI = MF.getFrameInfo();
const NuPlusInstrInfo &TII =
*static_cast<const NuPlusInstrInfo *>(MF.getSubtarget().getInstrInfo());
const MCRegisterInfo *MRI = MF.getMMI().getContext().getRegisterInfo();
MachineBasicBlock::iterator MBBI = MBB.begin();

// Debug location must be unknown since the first debug location is used
// to determine the end of the prologue.
DebugLoc DL;

// Compute stack size to allocate, keeping SP 64 byte aligned so we
// can do block vector load/stores
int StackSize = alignTo(MFI.getStackSize(), getStackAlignment());

// Bail if there is no stack allocation
if (StackSize == 0 && !MFI.adjustsStack())
return;

TII.adjustStackPointer(MBB, MBBI, DL, -StackSize);

// Emit DW_CFA_def_cfa
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);

// Find the instruction past the last instruction that saves a callee-saved
// register to the stack. We need to set up FP after its old value has been
// saved.
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
if (CSI.size()) {
for (unsigned i = 0; i < CSI.size(); ++i)
++MBBI;

// Iterate over list of callee-saved registers and emit .cfi_offset
// directives (debug information)
for (const auto &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
unsigned Reg = I.getReg();
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
}

// fp = sp
if (hasFP(MF)) {
BuildMI(MBB, MBBI, DL, TII.get(NuPlus::MOVE_SS_32))
.addReg(NuPlus::FP_REG)
.addReg(NuPlus::SP_REG);

// emit ".cfi_def_cfa_register $fp" (debug information)
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
nullptr, MRI->getDwarfRegNum(NuPlus::FP_REG, true)));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
}

void NuPlusFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
MachineFrameInfo &MFI = MF.getFrameInfo();
const NuPlusInstrInfo &TII =
*static_cast<const NuPlusInstrInfo *>(MF.getSubtarget().getInstrInfo());
DebugLoc DL = MBBI->getDebugLoc();
assert(MBBI->getOpcode() == NuPlus::JRET &&
"Can only put epilog before 'retl' instruction!");

// if framepointer enabled, restore the stack pointer.
if (hasFP(MF)) {
// Find the first instruction that restores a callee-saved register.
MachineBasicBlock::iterator I = MBBI;
for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i)
--I;

BuildMI(MBB, I, DL, TII.get(NuPlus::MOVE_SS_32))
.addReg(NuPlus::SP_REG)
.addReg(NuPlus::FP_REG);
}

uint64_t StackSize = alignTo(MFI.getStackSize(), getStackAlignment());
if (!StackSize)
return;

TII.adjustStackPointer(MBB, MBBI, DL, StackSize);
}

MachineBasicBlock::iterator NuPlusFrameLowering::eliminateCallFramePseudoInstr(
MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const {
MachineInstr &MI = *MBBI;

const NuPlusInstrInfo &TII =
*static_cast<const NuPlusInstrInfo *>(MF.getSubtarget().getInstrInfo());

// Note the check for hasReservedCallFrame. If it returns true,
// PEI::calculateFrameObjectOffsets has already reserved stack locations for
// these variables and we don't need to adjust the stack here.
int Amount = TII.getFrameSize(MI);
if (Amount != 0 && !hasReservedCallFrame(MF)) {
assert(hasFP(MF) &&
"Cannot adjust stack mid-function without a frame pointer");

if (MI.getOpcode() == NuPlus::ADJCALLSTACKDOWN)
Amount = -Amount;

TII.adjustStackPointer(MBB, MBBI, MBBI->getDebugLoc(), Amount);
}

return MBB.erase(MBBI);
}

void NuPlusFrameLowering::determineCalleeSaves(MachineFunction &MF,
BitVector &SavedRegs,
RegScavenger *RS) const {

TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
if (hasFP(MF))
SavedRegs.set(NuPlus::FP_REG);

// The register scavenger allows us to allocate virtual registers during
// epilogue/prologue insertion, after register allocation has run. We only
// need to do this if the frame is too large to be addressed by immediate
// offsets. If it isn't, don't bother creating a stack slot for it.
// This may create the scavenge slot when it isn't needed.
// This check must match the size of the one in
// NuPlusRegisterInfo::eliminateFrameIndex
if (isInt<9>(getWorstCaseStackSize(MF)))
return;

const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const TargetRegisterClass &RC = NuPlus::GPR32RegClass;
int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
TRI->getSpillAlignment(RC), false);
RS->addScavengingFrameIndex(FI);
}

// We must use an FP in a few situations. Note that this *must* return true if
// hasReservedCallFrame returns false. Otherwise an ADJCALLSTACKDOWN could mess
// up frame offsets from the stack pointer.
bool NuPlusFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
return MF.getTarget().Options.DisableFramePointerElim(MF) ||
MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
}

// Returns true if the prologue inserter should reserve space for outgoing
// arguments to called.
bool NuPlusFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
return !MF.getFrameInfo().hasVarSizedObjects();
}

uint64_t
NuPlusFrameLowering::getWorstCaseStackSize(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();

int64_t Offset = 0;

// Iterate over fixed sized objects.
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
Offset = std::max(Offset, -MFI.getObjectOffset(I));

// Conservatively assume all callee-saved registers will be saved.
for (const uint16_t *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(*R);
unsigned Size = TRI.getRegSizeInBits(*RC);
Offset = alignTo(Offset + Size, Size);
}

unsigned MaxAlign = MFI.getMaxAlignment();

// Check that MaxAlign is not zero if there is a stack object that is not a
// callee-saved spill.
assert(!MFI.getObjectIndexEnd() || MaxAlign);

// Iterate over other objects.
for (unsigned I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I)
Offset = alignTo(Offset + MFI.getObjectSize(I), MaxAlign);

// Call frame.
if (MFI.adjustsStack() && hasReservedCallFrame(MF))
Offset = alignTo(Offset + MFI.getMaxCallFrameSize(),
std::max(MaxAlign, getStackAlignment()));

return alignTo(Offset, getStackAlignment());
}

</syntaxhighlight>

NuPlusFrameLowering.cpp

2019-06-21T14:48:45Z

Francesco: Francesco moved page NuPlusFrameLowering.cpp to NaplesPUFrameLowering.cpp

#REDIRECT [[NaplesPUFrameLowering.cpp]]

NaplesPUISelLowering.cpp

2019-06-21T14:43:32Z

Francesco: Francesco moved page NuPlusISelLowering.cpp to NaplesPUISelLowering.cpp

=NuPlusTargetLowering class=
[[Category:C++ Classes]]
The '''NuPlusTargetLowering''' class implements the [http://llvm.org/docs/CodeGenerator.html#the-targetlowering-class TargetLowering] interface and is contained in the NuPlusISelLowering.h/.cpp files.
The class must describe how to lower LLVM code to machine code. This has two main components:
#Which ValueTypes are natively supported by the target.
#Which operations are supported for supported ValueTypes.

The '''NuPlusTargetLowering''' class can be thought of being composed by four sections:
#The class constructor.
#The custom [https://llvm.org/docs/CodeGenerator.html#introduction-to-selectiondags SDNode] lowering.
#The custom [http://llvm.org/docs/CodeGenerator.html#machineinstr MachineInstruction] insertion.
#The implementation of other TargetLowering virtual methods.

== The Class Constructor ==
The NuPlusTargetLowering class constructor describes the MachineValueTypes supported by nu+ with the corresponding [[NuPlusRegisterInfo.td |RegisterClass]], the operations not supported for supported MachineValueTypes and the corresponding action to perform, other useful information concerning the Instruction-Lowering phase.
These informations are described using the ''protected'' methods provided by the base class ''TargetLowering''.

=== addRegisterClass ===
The '''addRegisterClass''' method tells the Code Generator the supported MachineValueTypes and the RegisterClass to use. The '''MachineValueTypes''' are defined in the '''MVT''' class in "compiler/include/llvm/CodeGen/MachineValueType.h", while the RegisterClass are those defined in [[NuPlusRegisterInfo.td]]. The following table summarize the supported MachineValueTypes and the relative RegisterClass.

{| class="wikitable"
! style="font-weight: bold;" | RegisterClass
! style="font-weight: bold;" | MVT
|-
| GPR32RegClass
| i32, f32
|-
| GPR64RegClass
| i64, f64
|-
| VR512WRegClass
| v16i32, v16f32
|-
| VR512LRegClass
| v8i64, v8f64
|}

The corresponding code is:

<syntaxhighlight lang="c++" line='line'>
// Scalar data types
addRegisterClass(MVT::i32, &NuPlus::GPR32RegClass);
addRegisterClass(MVT::f32, &NuPlus::GPR32RegClass);

addRegisterClass(MVT::i64, &NuPlus::GPR64RegClass);
addRegisterClass(MVT::f64, &NuPlus::GPR64RegClass);

// Vector data types (512-bit wide)
addRegisterClass(MVT::v16i32, &NuPlus::VR512WRegClass);
addRegisterClass(MVT::v16f32, &NuPlus::VR512WRegClass);

addRegisterClass(MVT::v8i64, &NuPlus::VR512LRegClass);
addRegisterClass(MVT::v8f64, &NuPlus::VR512LRegClass);
</syntaxhighlight>

=== setOperationAction ===
The '''setOperationAction''' method is used to tell the Code Generator the unsupported operation for the specified MachineValueType and the action to perform, this because by default every operation is considered '''Legal'''.

This information is used by the LLVM Code Generator during the [http://llvm.org/docs/CodeGenerator.html#instruction-selection-section InstructionSelection] phase. So the input to give the function are the '''Operation Code''' (defined in the '''NodeType''' enum in "/compiler/include/llvm/CodeGen/ISDOpcodes.h"), the associated '''MachineValueTypes''' and the '''action''' to perform in order to legalize the operation. At this stage each operation is described by a Node in the SelectionDAG.

The action must be one of those in the '''LegalizeAction''' enum contained in the '''TargetLoweringBase''' class (/compiler/include/llvm/Target/TargetLowering.h). Hence the possible actions are:
* '''Legal''', the target natively supports this operation.
* '''Promote''', this operation should be executed in a larger type.
* '''Expand''', try to expand this to other ops, otherwise use a libcall.
* '''LibCall''', don't try to expand this to other ops, always use a libcall.
* '''Custom''', use the '''LowerOperation''' hook to implement custom lowering.

The most used in the nu++ backend are the ''Expand'' and the ''Custom'' actions.
As mentioned before, the '''Expand''' action tries to expand the node using equivalent operations, if this cannot be done, a function call is generated. The signature is defined in the '''InitLibcallNames''' in "/compiler/lib/CodeGen/TargetLoweringBase.cpp".
With the '''Custom''' action, the lowering must be manually done implementing a proper function.

== Custom Lowering ==

When an operation must be custom lowered (using setOperationAction with Custom action), LLVM calls the '''LowerOperation''' function passing it the Node to lower and the DAG. The lowering is handled in this way:
*The '''LowerOperation''' function is implemented with a switch on the Node Opcode, according to its value returns the SDValue of a specific function.
*The operand specific functions are named as ''LowerOPERAND_NAME'' and they must generate the Machine Nodes that correspond to the input Node (object of SDValue class).

=== Selection DAG Node representation ===
LLVM uses mainly three classes to represent a SelectionDAG: '''SDNode''' and '''SDValue''' and '''SDUse'''. They are defined in "/compiler/include/llvm/CodeGen/SelectionDAGNodes.h".

The '''SDNode''' class is the representation of a ''node'' in the Selection DAG and stores information about the operation type and its operands (list of SDUse objects).
The '''SDValue''' represents the output value of a SDNode. However, a SDNode may return muiltiple valuesas the result of a computation. Thus the SDValue stores informations about the SDNode as well as which return value to use from that node.
The '''SDUse''' class represents a a use of a SDNode and holds an SDValue, which records the SDNode being used and the result number, a pointer to the SDNode using the value, and Next and Prev pointers, which link together all the uses of an SDNode.

From a visual point of view, we can imagine a Selection DAG as composed by nodes and and edges.
A node has an operand list, an operation, an ID (all of them stored in a SDNode object) and one or more output values (each one represented by a SDValue object).
An arrow goes from an input operand to a return value (informations stored in a a SDUse object) and represents data flow among nodes. There are also "chain" edges that represent control flow and provide an ordering between nodes that have side effects such as loads, stores, calls, returns, etc.

It is possible to visualize, during a compilation, the DAGs LLVM generates by passing the flag "-mllvm -debug=isel" (textual form) or using the "-view*" options (visual form). Note that LLVM must be compiled in "Debug" mode in order to show such informations.

=== Lowering ===
The purpose of a custom lowering node function is to substitute the input node with a '''legal''' node or DAG that performs the same operation. The difference among a "legal" DAG and an "illegal" one, is that the legal DAG uses only operations an types supported by the machine.

For example lets analyze "LowerFNEG" function. It is used to lower the FNEG node using legal nodes.
The FNEG operation must perform the negation of a floating-point value (see "/compiler/include/llvm/CodeGen/ISDOpcodes.h" for definition). Since the nu+ architecture does not have an instruction to directly perform the operation, we have to perform the lowering manually.

The first step is to declare in the NuPlusTargetLowering class constructor that the FNEG operation must be custom lowered for all the supported floating-point types.

<syntaxhighlight lang="c++" line='line'>
// Note that this is just an example code. In nu+ backed
// we use for loops to make the file more readable.
setOperationAction(ISD::FNEG, MVT::f32, Custom);
setOperationAction(ISD::FNEG, MVT::f64, Custom);
setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
</syntaxhighlight>

Then we update the switch in the "LowerOperation" function so that calls the "LowerFNEG" function, previously defined in the NuPlusTargetLowering" interface (located in "/compiler/lib/Target/NuPlus/NuPlusISelLowering.h").

<syntaxhighlight lang="c++" line='line'>
SDValue NuPlusTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
...
case ISD::FNEG:
return LowerFNEG(Op, DAG);
...
}
</syntaxhighlight>

<syntaxhighlight lang="c++" line='line'>
class NuPlusTargetLowering : public TargetLowering {
public:
...
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
...
}
</syntaxhighlight>

Then we define the "LowerFNEG" function.

<syntaxhighlight lang="c++" line='line'>
SDValue NuPlusTargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT ResultVT = Op.getValueType().getSimpleVT();
MVT IntermediateVT;

if (ResultVT.isVector()) {
IntermediateVT =
(ResultVT.getVectorElementType() == MVT::f32) ? MVT::v16i32 : MVT::v8i64;
} else {
IntermediateVT =
(ResultVT.getScalarType() == MVT::f32) ? MVT::i32 : MVT::i64;
}

SDValue rhs = (IntermediateVT.getScalarType() == MVT::i32) ?
DAG.getConstant(0x80000000, DL, MVT::i32) :
DAG.getConstant(0x8000000000000000, DL, MVT::i64);

SDValue iconv;
if (ResultVT.isVector())
rhs = DAG.getNode(NuPlusISD::SPLAT, DL, IntermediateVT, rhs);

iconv = DAG.getNode(ISD::BITCAST, DL, IntermediateVT, Op.getOperand(0));
SDValue flipped = DAG.getNode(ISD::XOR, DL, IntermediateVT, iconv, rhs);
return DAG.getNode(ISD::BITCAST, DL, ResultVT, flipped);
}

</syntaxhighlight>

The two inputs are "SDValue Op" and "SelectionDAG &DAG". '''Op''' is the node that must be lowered, in this case an FNEG operation. It is a SDValue object because in this way we have also information about the output value. '''DAG''' is used to create the nodes containing the operations the one contained in '''Op'''.

[[File:FNEGScalar.png|frame|This image shows how the FNEG is lowered in case of scalar floating-point value.]]
[[File:FNEGVector.png|frame|This image shows how the FNEG is lowered in case of vector floating-point value. Differently from the scalar case, the SPLAT node is added before the XOR.]]

The function must return the last of the legal nodes generated. The figures belove show lowering of FNEG node.

According to the IEEE 754 standard the MSB is the sign bit, thus to negate a floating-point value the MSB must be inverted. This could be done by XORing the floating-point value with 0x80000000 (for 32-bit floating-point) or 0x8000000000000000 (for 64-bit floating-point).
The XOR operation, however, can only be done between integer operations. Thus floating-point operand must be bitcasted into an integer before XORing it. The bitcast operation tells LLVM to interpret a value with a different type with same width (e.g. i32 <-> f32). The inverse bistacst operation need to be done also for the XOR return value that must be interpreted as a floating-point.

In case of the FNEG is done on a vector type, we must add another node to correctly load the constant 0x80000000 (or 0x8000000000000000). This is done through the SPLAT operation. This operation takes a scalar and copies it on all the vector elements. In hardware it corresponds to a move operation.

The function code first checks the result type, in order to determine the appropriate integer type for the constant and XOR operation (It is stored in the "IntermediateVT" variable).
Then we use the "getConstant" method to generate the Constant Node. The method takes the constant value, a SDLoc object containing the '''Op''' IR location info and the value type.

If the input operand type is a vector, we generate a SPLAT node.
Then we create the XOR node preceded and succeeded by the SPLAT operations.

The method "getNode" is used to generate nodes. It takes the node Opcode, the SDLoc object, the output value type and the input operands. The function returns only the SDValue of the last BITCAST operation since it stores the informations about the previous nodes.

The SPLAT node does not belong to the "ISD" namespace but to the "NuPlusISD" namespace. This because LLVM does not have this node type and is defined only in the nu+ back-end. It will be resolved later during the Select phase using one of the patterns defined in [[NuPlusInstrInfo.td]].

The other lowering functions act in a similar way. They lower the input node using the SelectionDAG class methods according to the operation to implement and the input node informations.
However, there are cases in which nodes tagged to be custom lowered are simply expanded. This is done, for example, in the "LowerBUILD_VECTOR" function in which the BUILD_VECTOR node must be lowered with a SPLAT operation only if the vector it tries to build is composed by the same scalar value, otherwise the expansion of the BUILD_VECTOR node is sufficient.

The way to tell the Code Generator that the node must be expanded is to return an empty SDValue.

<syntaxhighlight lang="c++" line='line'>
SDValue NuPlusTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
// MVT VT = Op.getValueType().getSimpleVT();
SDLoc DL(Op);

if (isSplatVector(Op.getNode())) {
// This is a constant node that is duplicated to all lanes.
// Convert it to a SPLAT node.
return CheckSplat(Op, Op.getOperand(0), DAG);
}

return SDValue(); // Expand
}

</syntaxhighlight>

== Custom MachineInstruction Insertion ==

Another way to lower unsupported operations is to manually emit Machine Instructions. The emission of Machine Instructions takes place just before the '''Register Allocation'''. It is important to remember that the Machine Instructions are still in SSA form, so care must be taken when creating virtual registers.

To instruct LLVM about what operations must have a custom inserter, a (pseudo)instruction in [[NuPlusInstrInfo.td]] with the '''usesCustomInserter''' flag setted to 1 must be defined.

When an MachineInstruction must be custom inserted, LLVM calls the '''EmitInstrWithCustomInserter''' function passing it the Machine Instruction to lower and the Basic Block, the instruction belongs:
*The '''EmitInstrWithCustomInserter''' function is implemented with a switch on the Machine Instruction Opcode, according to its value returns the modified input basic block.
*The operand specific functions are named as ''EmitOPERATION_NAME'' and they must generate the instructions that correspond to the input Machine Instruction.

=== Instruction Insertion ===
The purpose of a custom instruction inserter function is to substitute the input Machine Instruction with instructions that perform the same operation.

For example, lets consider the "EmitLoadI32" function.

In nu+, the immediate field of type I instruction is 16 bits wide so to load a 32-bit immediate value the instruction couple MOVEIH-MOVEIL must be emitted.

The EmitLoadI32 function is called by the EmitInstrWithCustomInserter hook function. The latter is called when the Code Generator encounters a machine instruction which has the usesCustomInserter flag setted to 1.

Therefore, in NuPlusInstrInfo.td, the pseudo-instruction '''LoadI32''' is defined with usesCustomInserter = 1. The corresponding node is generated during the Select phase, when the pattern "(set i32:$dst, (i32 imm:$val))" is detected.

<syntaxhighlight lang="c++" line='line'>
let usesCustomInserter = 1 in {
def LoadI32 : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$val),
[(set i32:$dst, (i32 imm:$val))]>;

...

}
</syntaxhighlight>

When must emit the instruction corresponding to '''LoadI32''', the "EmitLoadI32" is called (through the EmitInstrWithCustomInserter hook function).
The emit functions have at least two inputs ([http://llvm.org/docs/CodeGenerator.html#the-machineinstr-class MachineInstr] *MI and [http://llvm.org/docs/CodeGenerator.html#the-machinebasicblock-class MachineBasicBlock] *BB) and must return the MachineBasicBlock modified.

To emit instructions the '''BuildMI''' interface (defined in "/compiler/include/llvm/CodeGen/MachineInstrBuilder.h") is used. This interface allows a simple way to generate instructions, providing methods like addReg, addImm and etc.

In the case of the EmitLoadI32, first the immediate values is taken from the LoadI32 operation, then the InsertLoad32Immediate function is called. This function is responsible of generating the MOVEIH-MOVEIL instruction couple. At last LoadI32 is deleted and the resulting Basic Block is returned.

<syntaxhighlight lang="c++" line='line'>
MachineBasicBlock *
NuPlusTargetLowering::EmitLoadI32(MachineInstr *MI,
MachineBasicBlock *BB) const {

DebugLoc DL = MI->getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();

// Get the integer immediate value.
int64_t ImmOp = MI->getOperand(1).getImm();
// Call the fuction that generates the MIs.
InsertLoad32Immediate(MI, BB, TII, &DL, MI->getOperand(0).getReg(), ImmOp);

MI->eraseFromParent();

return BB;
}
</syntaxhighlight>

The InsertLoad32Immediate function uses the BuildMI interface to generate the instructions. There are several versions of BuildMI, the one used takes as inputs the MachineBasicBlock where to insert the instructions, the pointer to the MachineInstruction before which insert the new instruction, a DebugLoc and the instruction description (MCInstrDesc class object) it must generate.
The instruction description is obtained through the TargetInstrInfo get method passing it the instruction name.

Note: in a Machine Instruction the first operand is the output.

<syntaxhighlight lang="c++" line='line'>
void InsertLoad32Immediate (MachineInstr *MI, MachineBasicBlock *BB,
const TargetInstrInfo *TII, DebugLoc *DL,
unsigned DestReg, int64_t Immediate) {

BuildMI(*BB, *MI, *DL, TII->get(NuPlus::MOVEIHSI))
.addReg(DestReg, RegState::Define)
.addImm(((Immediate >> 16) & 0xFFFF));
BuildMI(*BB, *MI, *DL, TII->get(NuPlus::MOVEILSI))
.addReg(DestReg)
.addImm((Immediate & 0xFFFF));

}
</syntaxhighlight>

Since the instruction are still in SSA form, the code above shows a workaround to use the same destination register.

== Other Methods ==

The NuPlusTargetLowering class redefines also some other methods used to instruct the Code Generator about the specific capabilities supported or unsupported by the nu+ architecture.

NuPlusISelLowering.cpp

2019-06-21T14:43:32Z

Francesco: Francesco moved page NuPlusISelLowering.cpp to NaplesPUISelLowering.cpp

#REDIRECT [[NaplesPUISelLowering.cpp]]

NaplesPUInstrFormats.td

2019-06-21T14:42:50Z

Francesco: Francesco moved page NuPlusInstrFormats.td to NaplesPUInstrFormats.td

[[Category:Tablegen Files]]
The NuPlusInstrFormats.td contains the classes that describe the [[ISA|nu+ instruction formats]], support classes to facilitate the instructions definition and also the definition nodes which make the pattern recognition easier.

<syntaxhighlight>
//===-- NuPlusInstrFormats.td - NuPlus Instruction Formats ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//

def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
def simm9 : PatLeaf<(imm), [{ return isInt<9>(N->getSExtValue()); }]>;

// Addressing modes as in SPARC
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
def V16ADDRri : ComplexPattern<v16i32, 2, "SelectADDRri", [], []>;
def V8ADDRri : ComplexPattern<v8i64, 2, "SelectADDRri", [], []>;

//===----------------------------------------------------------------------===//
// NuPlus profiles and nodes
//===----------------------------------------------------------------------===//
// Transformation nodes
def LO32I : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getAPIntValue().getLoBits(32).getZExtValue(), SDLoc(N), MVT::i32);}]>;

def HI32I : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return CurDAG->getTargetConstant((unsigned)N->getAPIntValue().getHiBits(32).getZExtValue(), SDLoc(N), MVT::i32);}]>;

def LO32F : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant((unsigned)(N->getValueAPF().bitcastToAPInt().getLoBits(32).getZExtValue()), SDLoc(N), MVT::i32);}]>;

def HI32F : SDNodeXForm<fpimm, [{
// Transformation function: shift the immediate value down into the low bits.
return CurDAG->getTargetConstant((unsigned)(N->getValueAPF().bitcastToAPInt().getHiBits(32).getZExtValue()), SDLoc(N), MVT::i32);}]>;

def DIV2 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() / 2, SDLoc(N), MVT::i32);}]>;

// Moveil/moveih nodes definition, used for globaladdress lowering
def leah : SDNode<"NuPlusISD::LEAH", SDTypeProfile<1, 1, []>>;
def leal : SDNode<"NuPlusISD::LEAL", SDTypeProfile<1, 2, []>>;

// A splat is a vector with the same value in all lanes. Used to handle operation
// with both vector and scalar operands.
def splat : SDNode<"NuPlusISD::SPLAT", SDTypeProfile<1, 1, [SDTCisEltOfVec<1, 0>]>>;

def return : SDNode<"NuPlusISD::RET_FLAG", SDTypeProfile<0, 0, []>,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;

def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;

def call : SDNode<"NuPlusISD::CALL", SDT_SPCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;

//To mark the beginning and end of a call sequence
def SDT_SPCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
def SDT_SPCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
[SDNPHasChain, SDNPSideEffect,
SDNPOptInGlue, SDNPOutGlue]>;
//To handle the lack of conditional moves
def selcondresult : SDNode<"NuPlusISD::SEL_COND_RESULT", SDTypeProfile<1, 3,
[SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>>;

//===----------------------------------------------------------------------===//
// Operand Definitions
//===----------------------------------------------------------------------===//

// Used for the LEA_Sym, to detect the lea pseudo instruction
def symref : Operand<OtherVT> {}

def SIMM16OP : Operand<i32> {
let DecoderMethod = "decodeSimm16Value";
}

def SIMM9OP : Operand<i32> {
let DecoderMethod = "decodeSimm9Value";
}

def MemAsmOperand : AsmOperandClass {
let Name = "Mem";
let ParserMethod = "ParseMemoryOperand";
}

def MEMri : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeMemoryOpValue";
let DecoderMethod = "decodeScalarMemoryOpValue";
let ParserMatchClass = MemAsmOperand;
let MIOperandInfo = (ops GPR32, i32imm);
}

def V16MEMri : Operand<v16i32> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeMemoryOpValue";
let DecoderMethod = "decodeVectorWMemoryOpValue";
let ParserMatchClass = MemAsmOperand;
let MIOperandInfo = (ops VR512W, i32imm);
}

def LEAri : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeLEAValue";
let ParserMatchClass = MemAsmOperand; //TODO: controllare se è corretto il ParserMatchClass
let MIOperandInfo = (ops GPR32, i32imm);
}

def ABSh : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeABShValue";
let ParserMatchClass = MemAsmOperand; //TODO: controllare se è corretto il ParserMatchClass
let MIOperandInfo = (ops i32imm);
}

def ABSl : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let EncoderMethod = "encodeABSlValue";
let ParserMatchClass = MemAsmOperand; //TODO: controllare se è corretto il ParserMatchClass
let MIOperandInfo = (ops i32imm);
}

def brtarget : Operand<OtherVT>
{
let EncoderMethod = "encodeBranchTargetOpValue";
let DecoderMethod = "decodeBranchTargetOpValue";
}

def calltarget : Operand<iPTR>
{
let EncoderMethod = "encodeBranchTargetOpValue";
let DecoderMethod = "decodeBranchTargetOpValue";
}

//===----------------------------------------------------------------------===//
// Pattern fragments
//===----------------------------------------------------------------------===//
// Definition of anyextload used in the loading of vector types < 512 bits
def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr),
[{ return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;}]>;

//----------------------------------------------------------------------------//
//------------------------------ LOAD AND STORE ------------------------------//
//----------------------------------------------------------------------------//

def MemStore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return !cast<StoreSDNode>(N)->isTruncatingStore();
else
return false;}]>;

def MemLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
else
return false;}]>;

def ScratchpadStore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return !cast<StoreSDNode>(N)->isTruncatingStore();
else
return false;}]>;

def ScratchpadLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
else
return false;}]>;

//---------------- EXTLOAD scalar ----------------//
def extloadi1_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def extloadi1_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def extloadi8_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def extloadi8_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def extloadi16_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def extloadi16_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def extloadi32_mem : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def extloadi32_scratch : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- ZEXTLOAD scalar ----------------//
def zextloadi1_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def zextloadi1_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def zextloadi8_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def zextloadi8_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def zextloadi16_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def zextloadi16_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def zextloadi32_mem : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def zextloadi32_scratch : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- ZEXTLOAD vector ----------------//
def zextloadv16i8_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def zextloadv16i8_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def zextloadv16i16_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def zextloadv16i16_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def zextloadv8i8_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def zextloadv8i8_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def zextloadv8i16_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def zextloadv8i16_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def zextloadv8i32_mem: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def zextloadv8i32_scratch: PatFrag<(ops node:$ptr), (zextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

//---------------- SEXTLOAD scalar ----------------//
def sextloadi1_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def sextloadi1_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def sextloadi8_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def sextloadi8_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def sextloadi16_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def sextloadi16_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def sextloadi32_mem : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def sextloadi32_scratch : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- SEXTLOAD vector ----------------//
def sextloadv16i8_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def sextloadv16i8_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def sextloadv16i16_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def sextloadv16i16_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def sextloadv8i8_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def sextloadv8i8_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def sextloadv8i16_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def sextloadv8i16_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def sextloadv8i32_mem: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def sextloadv8i32_scratch: PatFrag<(ops node:$ptr), (sextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

//---------------- ANYEXTLOAD vector ----------------//
def anyextloadv16i8_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def anyextloadv16i8_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def anyextloadv16i16_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def anyextloadv16i16_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def anyextloadv8i8_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def anyextloadv8i8_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def anyextloadv8i16_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def anyextloadv8i16_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def anyextloadv8i32_mem: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() != 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def anyextloadv8i32_scratch: PatFrag<(ops node:$ptr), (anyextload node:$ptr),
[{ if(cast<LoadSDNode>(N)->getAddressSpace() == 77)
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

//---------------- TRUNCSTORE scalar ----------------//
def truncstorei1_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;
def truncstorei1_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
else
return false;}]>;

def truncstorei8_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;
def truncstorei8_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
else
return false;}]>;

def truncstorei16_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;
def truncstorei16_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
else
return false;}]>;

def truncstorei32_mem : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;
def truncstorei32_scratch : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
else
return false;}]>;

//---------------- TRUNCSTORE vector ----------------//
def truncstorev16i8_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;
def truncstorev16i8_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i8;
else
return false; }]>;

def truncstorev16i16_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;
def truncstorev16i16_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v16i16;
else
return false; }]>;

def truncstorev8i8_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;
def truncstorev8i8_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i8;
else
return false; }]>;

def truncstorev8i16_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;
def truncstorev8i16_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i16;
else
return false; }]>;

def truncstorev8i32_mem: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;
def truncstorev8i32_scratch: PatFrag<(ops node:$val, node:$ptr), (truncstore node:$val, node:$ptr),
[{ if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v8i32;
else
return false; }]>;

// insertelt SDNode redefinition
def VecInsert : SDTypeProfile<1, 3, [ // vector insert
SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
]>;

def insert_elt : SDNode<"ISD::INSERT_VECTOR_ELT", VecInsert>;

//===----------------------------------------------------------------------===//
// Describe NuPlus Special Registers
//
//
//===----------------------------------------------------------------------===//

class SpReg<bits<6> reg> {
bits<6> Register = reg;
}

def MaskReg : SpReg<59>;

//===----------------------------------------------------------------------===//
// Describe NuPlus scalar or vector instructions
//
// Fmt - 0 if a register is scalar, 1 if vector
//===----------------------------------------------------------------------===//

class Fmt<bit val> {
bit Value = val;
}

def Fmt_S : Fmt<0>;
def Fmt_V : Fmt<1>;

//===----------------------------------------------------------------------===//
// Describe NuPlus instructions format here
//===----------------------------------------------------------------------===//

class InstNuPlus<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
field bits<32> Inst;

let Namespace = "NuPlus";
let Size = 4;

dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;

//let DecoderNamespace = "NuPlus";
field bits<32> SoftFail = 0;
}

//===----------------------------------------------------------------------===//
// Format R instruction class in NuPlus : <00|opcode|rd|rs0|rs1|unused|l|fmt|m|>
// l: if 1, 64 bit mode
// fmt2: FMT value for rd register
// fmt1: FMT value for rs0 register
// fmt0: FMT value for rs1 register
// m: if 1, masked
//
//===----------------------------------------------------------------------===//

class FR<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0, bit m>
: InstNuPlus<outs, ins, asmstr, pattern> {
bits <6> dst;
bits <6> src0;

let Inst{31-30} = 0;
let Inst{29-24} = opcode;
let Inst{23-18} = dst;
let Inst{17-12} = src0;
let Inst{5} = 0; //unused
let Inst{4} = l;
let Inst{3} = fmt2.Value;
let Inst{2} = fmt1.Value;
let Inst{1} = fmt0.Value;
let Inst{0} = m;
}

class FR_TwoOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0, bit m>
: FR<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, m> {
bits <6> src1;

let Inst{11-6} = src1;
}

class FR_OneOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0, bit m>
: FR<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, m> {

let Inst{11-6} = 0;
}

class FR_TwoOp_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, 1> {
let Uses = [MR_REG];
}

class FR_TwoOp_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, fmt0, 0> {

}

class FR_OneOp_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1>
: FR_OneOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, Fmt_S, 1> {
let Uses = [MR_REG];
}

class FR_OneOp_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, Fmt fmt2, Fmt fmt1>
: FR_OneOp<outs, ins, asmstr, pattern, opcode, l, fmt2, fmt1, Fmt_S, 0> {

}

class FR_TwoOp_Masked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Masked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1, fmt0> {

}

class FR_TwoOp_Masked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Masked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1, fmt0> {

}

class FR_TwoOp_Unmasked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Unmasked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1, fmt0> {

}

class FR_TwoOp_Unmasked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp_Unmasked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1, fmt0> {

}

class FR_OneOp_Masked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Masked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1> {

}

class FR_OneOp_Masked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Masked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1> {

}

class FR_OneOp_Unmasked_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Unmasked<outs, ins, asmstr, pattern, opcode, 0, fmt2, fmt1> {

}

class FR_OneOp_Unmasked_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1>
: FR_OneOp_Unmasked<outs, ins, asmstr, pattern, opcode, 1, fmt2, fmt1> {

}

//===----------------------------------------------------------------------===//
// Format I instruction class in NuPlus : <010|opcode|rd|rs|imm|fmt|m|>
// fmt1: FMT value for rd register
// fmt0: FMT value for rs register
// m: if 1 masked
//===----------------------------------------------------------------------===//

class FI<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0, bit m>
: InstNuPlus<outs, ins, asmstr, pattern> {
bits <6> dst;
bits <9> imm;

let Inst{31-29} = 0b010;
let Inst{28-24} = opcode;
let Inst{23-18} = dst;
let Inst{11-3} = imm;
let Inst{2} = fmt1.Value;
let Inst{1} = fmt0.Value;
let Inst{0} = m;
}

class FI_OneOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0, bit m> : FI<outs, ins, asmstr, pattern, opcode, fmt1, fmt0, m> {
bits <6> src;

let Inst{17-12} = src;
}

class FI_NoOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1> : FI<outs, ins, asmstr, pattern, opcode, fmt1, Fmt_S, 0> {
let Inst{17-12} = 0;
}

class FI_OneOp_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0> : FI_OneOp<outs, ins, asmstr, pattern, opcode, fmt1, fmt0, 1> {
let Uses = [MR_REG];
}

class FI_OneOp_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<5> opcode, Fmt fmt1, Fmt fmt0> : FI_OneOp<outs, ins, asmstr, pattern, opcode, fmt1, fmt0, 0> {

}

//===----------------------------------------------------------------------===//
// Format MOVEI instruction class in NuPlus : <01100|opcode|rd|imm|fmt|m|>
//===----------------------------------------------------------------------===//

class FMOVEI<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode, Fmt fmt, bit m>
: InstNuPlus<outs, ins, asmstr, pattern> {
bits <6> dst;
bits <16> imm;

let Inst{31-27} = 0b01100;
let Inst{26-24} = opcode;
let Inst{23-18} = dst;
let Inst{17-2} = imm;
let Inst{1} = fmt.Value;
let Inst{0} = m;
}

//===----------------------------------------------------------------------===//
// Format M instruction class in NuPlus : <10|opcode|rd/rs|rptr|off|l|s|m|>
//===----------------------------------------------------------------------===//

class FM<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, bit s, bit m>
: InstNuPlus<outs, ins, asmstr, pattern> {
bits <6> dstsrc;
bits <15> addr; //base address and offset encoded on the same 15 bits value (check encodeMemoryOpValue)

let Inst{31-30} = 0b10;
let Inst{29-24} = opcode;
let Inst{23-18} = dstsrc;
let Inst{17-12} = addr{5-0};
let Inst{11-3} = addr{14-6};
let Inst{2} = l;
let Inst{1} = s;
let Inst{0} = m;
}

class FM_Unmasked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, bit s>
: FM<outs, ins, asmstr, pattern, opcode, l, s, 0> {
}

class FM_Masked<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l, bit s>
: FM<outs, ins, asmstr, pattern, opcode, l, s, 1> {
let Uses = [MR_REG];
}

class FM_Unmasked_Mainmem<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Unmasked<outs, ins, asmstr, pattern, opcode, l, 0> {
}

class FM_Unmasked_Scratchpad<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Unmasked<outs, ins, asmstr, pattern, opcode, l, 1> {
}

class FM_Masked_Mainmem<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Masked<outs, ins, asmstr, pattern, opcode, l, 0> {
}

class FM_Masked_Scratchpad<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, bit l>
: FM_Masked<outs, ins, asmstr, pattern, opcode, l, 1> {
}

class FM_Unmasked_Mainmem_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Mainmem<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Unmasked_Scratchpad_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Scratchpad<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Masked_Mainmem_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Mainmem<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Masked_Scratchpad_32<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Scratchpad<outs, ins, asmstr, pattern, opcode, 0> {
}

class FM_Unmasked_Mainmem_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Mainmem<outs, ins, asmstr, pattern, opcode, 1> {
}

class FM_Unmasked_Scratchpad_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Unmasked_Scratchpad<outs, ins, asmstr, pattern, opcode, 1> {
}

class FM_Masked_Mainmem_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Mainmem<outs, ins, asmstr, pattern, opcode, 1> {
}

class FM_Masked_Scratchpad_64<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode>
: FM_Masked_Scratchpad<outs, ins, asmstr, pattern, opcode, 1> {
}

//===----------------------------------------------------------------------===//
// Format J/BR instruction class in NuPlus
// FJR: <0111|type(0/1)|opcode|rd|imm|>
// FJ: <0111|type(0/1)|opcode|imm|>
//===----------------------------------------------------------------------===//

class FJ_ALL<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: InstNuPlus<outs, ins, asmstr, pattern> {

let Inst{31-28} = 0b0111;
let Inst{26-24} = opcode;
let isBranch = 1;
}

class FJR<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: FJ_ALL<outs, ins, asmstr, pattern, opcode> {
bits <6> cond;
bits <18> addr;

let Inst{27} = 0;
let Inst{23-18} = cond;
let Inst{17-0} = addr;
}

class FJ<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: FJ_ALL<outs, ins, asmstr, pattern, opcode> {
bits <24> addr;

let Inst{27} = 1;
let Inst{23-0} = addr;
}

//===----------------------------------------------------------------------===//
// Format C instruction class in NuPlus
// FC: <01101|opcode|rs0|rs1|unused|>
//===----------------------------------------------------------------------===//

class FC<dag outs, dag ins, string asmstr, list<dag> pattern, bits<3> opcode>
: InstNuPlus<outs, ins, asmstr, pattern> {

bits <6> src0;
bits <6> src1;

let Inst{31-27} = 0b01101;
let Inst{26-24} = opcode;
let Inst{23-18} = src0;
let Inst{17-12} = src1;
let Inst{11-0} = 0; //unused
}

//===----------------------------------------------------------------------===//
// A set of multiclasses is used to handle Vector/Scalar combinations
// SS: Scalar = Op Scalar
// VV: Vector = Op Vector
// SI: Vector = Op Immediate
// SSS: Scalar = Scalar Op Scalar
// VVS: Vector = Vector Op Scalar
// VVV: Vector = Vector Op Vector
// SVV: Scalar = Vector Op Vector
// SSI: Scalar = Vector Op Immediate
// VVI: Scalar = Vector Op Immediate
//===----------------------------------------------------------------------===//

multiclass FArithInt_TwoOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SSS - 32 bit integer
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (OpNode i32:$src0, i32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - VVS unmasked - 32 bit integer
def VVS_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV unmasked - 32 bit integer
def VVV_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, v16i32:$src1))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VVS masked - 32 bit integer
def VVS_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV masked - 32 bit integer
def VVV_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src0, v16i32:$src1),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

}
// FI - SSI
def SSI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins GPR32:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (OpNode i32:$src, (i32 simm9:$imm)))],
opcode{4-0},
Fmt_S,
Fmt_S>;

// FI - VVI unmasked
def VVI_U : FI_OneOp_Unmasked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set v16i32:$dst, (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))))],
opcode{4-0},
Fmt_V,
Fmt_V>;

// FI - VVI masked
let Constraints = "$dst = $oldvalue" in {
def VVI_M : FI_OneOp_Masked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm, VR512W:$oldvalue),
operator # "i.m $dst, $src, $imm",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))), v16i32:$oldvalue))],
opcode{4-0},
Fmt_V,
Fmt_V>;
}
}

multiclass FArithInt_OneOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SS - 32 bit integer
def SS_32 : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
operator # "_i32 $dst, $src0",
[(set i32:$dst, (OpNode i32:$src0))],
opcode,
Fmt_S,
Fmt_S>;

// FR - VV unmasked - 32 bit integer
def VV_U_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
operator # "_i32 $dst, $src0",
[(set v16i32:$dst, (OpNode v16i32:$src0))],
opcode,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VV masked - 32 bit integer
def VV_M_32 : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src0),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V>;

}
}

// per la shift rotate
multiclass FSRInt_TwoOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SSS - 32 bit integer
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (OpNode i32:$src0, i32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - VVS unmasked - 32 bit integer
def VVS_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV unmasked - 32 bit integer
def VVV_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set v16i32:$dst, (OpNode v16i32:$src0, v16i32:$src1))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VVS masked - 32 bit integer
def VVS_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src0, (v16i32 (splat i32:$src1))),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV masked - 32 bit integer
def VVV_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0, $src1",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src0, v16i32:$src1),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

}
// FI - SSI
def SSI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins GPR32:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (OpNode i32:$src, (i32 simm9:$imm)))],
opcode{4-0},
Fmt_S,
Fmt_S>;

// FI - VVI unmasked
def VVI_U : FI_OneOp_Unmasked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set v16i32:$dst, (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))))],
opcode{4-0},
Fmt_V,
Fmt_V>;

// FI - VVI masked
let Constraints = "$dst = $oldvalue" in {
def VVI_M : FI_OneOp_Masked<
(outs VR512W:$dst),
(ins VR512W:$src, SIMM9OP:$imm, VR512W:$oldvalue),
operator # "i.m $dst, $src, $imm",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src, (v16i32 (splat simm9:$imm))), v16i32:$oldvalue))],
opcode{4-0},
Fmt_V,
Fmt_V>;
}
}

multiclass FArithFloat_TwoOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SSS - 32 bit float
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set f32:$dst, (OpNode f32:$src0, f32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - VVS unmasked - 32 bit float
def VVS_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set v16f32:$dst, (OpNode v16f32:$src0, (splat f32:$src1)))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV unmasked - 32 bit float
def VVV_U_32 : FR_TwoOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set v16f32:$dst, (OpNode v16f32:$src0, v16f32:$src1))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VVS masked - 32 bit float
def VVS_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, GPR32:$src1, VR512W:$oldvalue),
operator # "_f32.m $dst, $src0, $src1",
[(set v16f32:$dst, (int_nuplus_vector_mixf32 (OpNode v16f32:$src0, (splat f32:$src1)),
v16f32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_S>;

// FR - VVV masked - 32 bit float
def VVV_M_32 : FR_TwoOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$src1, VR512W:$oldvalue),
operator # "_f32.m $dst, $src0, $src1",
[(set v16f32:$dst, (int_nuplus_vector_mixf32 (OpNode v16f32:$src0, v16f32:$src1),
v16f32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V,
Fmt_V>;
}
}

multiclass FArithFloat_OneOp<string operator, SDNode OpNode, bits<6> opcode> {
// FR - SS - 32 bit float
def SS_32 : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
operator # "_f32 $dst, $src0",
[(set f32:$dst, (OpNode f32:$src0))],
opcode,
Fmt_S,
Fmt_S>;

// FR - VV unmasked - 32 bit float
def VV_U_32 : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
operator # "_f32 $dst, $src0",
[(set v16f32:$dst, (OpNode v16f32:$src0))],
opcode,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VV masked - 32 bit float
def VV_M_32 : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
operator # "_f32.m $dst, $src0",
[(set v16f32:$dst, (int_nuplus_vector_mixi32 (OpNode v16i32:$src0),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V>;
}
}

// Condition codes defined in include/llvm/CodeGen/ISDOpcodes.h
// VS and VV comparisons are handled through intrinsics
multiclass FCompInt<string operator, CondCode condition,
bits<6> opcode, Intrinsic vectorIntr32> {
// FR - SSS - 32 bit integer
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (setcc i32:$src0, i32:$src1, condition))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - SVS unmasked - 32 bit integer
def SVS_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16i32:$src0, (splat i32:$src1)))],
opcode,
Fmt_S,
Fmt_V,
Fmt_S>;

// FR - SVV unmasked - 32 bit integer
def SVV_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16i32:$src0, v16i32:$src1))],
opcode,
Fmt_S,
Fmt_V,
Fmt_V>;

// FI - SSI
def SSI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins GPR32:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (setcc i32:$src, simm9:$imm, condition))],
opcode{4-0},
Fmt_S,
Fmt_S>;

// FI - SVI unmasked
def SVI : FI_OneOp_Unmasked<
(outs GPR32:$dst),
(ins VR512W:$src, SIMM9OP:$imm),
operator # "i $dst, $src, $imm",
[(set i32:$dst, (vectorIntr32 v16i32:$src, (splat simm9:$imm)))],
opcode{4-0},
Fmt_S,
Fmt_V>;
}

multiclass FCompFloat<string operator, SDNode OpNode,
bits<6> opcode, Intrinsic vectorIntr32> {
// FR - SSS - 32 bit float
def SSS_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set i32:$dst, (OpNode f32:$src0, f32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;

// FR - SVS unmasked - 32 bit float
def SVS_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, GPR32:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16f32:$src0, (splat f32:$src1)))],
opcode,
Fmt_S,
Fmt_V,
Fmt_S>;

// FR - SVV unmasked - 32 bit float
def SVV_U_32 : FR_TwoOp_Unmasked_32<
(outs GPR32:$dst),
(ins VR512W:$src0, VR512W:$src1),
operator # "_f32 $dst, $src0, $src1",
[(set i32:$dst, (vectorIntr32 v16f32:$src0, v16f32:$src1))],
opcode,
Fmt_S,
Fmt_V,
Fmt_V>;

}

multiclass FSext_32<string operator, ValueType vt,
bits<6> opcode, ValueType vt_v> {
// FR - SS
def SS : FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins GPR32:$src0),
operator # "_i32 $dst, $src0",
[(set i32:$dst, (sext_inreg i32:$src0, vt))],
opcode,
Fmt_S,
Fmt_S>;

// FR - VV unmasked
def VV_U : FR_OneOp_Unmasked_32<
(outs VR512W:$dst),
(ins VR512W:$src0),
operator # "_i32 $dst, $src0",
[(set v16i32:$dst, (sext vt_v:$src0))],
opcode,
Fmt_V,
Fmt_V>;

let Constraints = "$dst = $oldvalue" in {
// FR - VV masked
def VV_M : FR_OneOp_Masked_32<
(outs VR512W:$dst),
(ins VR512W:$src0, VR512W:$oldvalue),
operator # "_i32.m $dst, $src0",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (sext vt_v:$src0),
v16i32:$oldvalue))],
opcode,
Fmt_V,
Fmt_V>;
}
}

//===----------------------------------------------------------------------===//
// A set of multiclasses used to handle Loads and Stores
//===----------------------------------------------------------------------===//

// Scalar LOAD
multiclass FMLoadScalar_32<string suffix, PatFrag op_mem, PatFrag op_scratch, bits<6> opcode> {

def _Mainmem : FM_Unmasked_Mainmem<
(outs GPR32:$dstsrc),
(ins MEMri:$addr),
"load32" # suffix # " $dstsrc, $addr",
[(set i32:$dstsrc, (i32 (op_mem ADDRri:$addr)))],
opcode,
0>;

def _Scratchpad : FM_Unmasked_Scratchpad<
(outs GPR32:$dstsrc),
(ins MEMri:$addr),
"load32" # suffix # "_scratchpad $dstsrc, $addr",
[(set i32:$dstsrc, (i32 (op_scratch ADDRri:$addr)))],
opcode,
0>;

}

// Scalar STORE
multiclass FMStoreScalar_32<string suffix, PatFrag op_mem, PatFrag op_scratch, bits<6> opcode> {

def _Mainmem : FM_Unmasked_Mainmem<
(outs),
(ins GPR32:$dstsrc, MEMri:$addr),
"store32" # suffix # " $dstsrc, $addr",
[(op_mem i32:$dstsrc, ADDRri:$addr)],
opcode,
0>;

def _Scratchpad : FM_Unmasked_Scratchpad<
(outs),
(ins GPR32:$dstsrc, MEMri:$addr),
"store32" # suffix # "_scratchpad $dstsrc, $addr",
[(op_scratch i32:$dstsrc, ADDRri:$addr)],
opcode,
0>{
let hasSideEffects = 1;
let mayStore = 1;
}
}

// Vector LOAD
multiclass FMLoadVector_32<string suffix, PatFrag op_Umem, PatFrag op_Uscratch,
Intrinsic op_Mmem, Intrinsic op_Mscratch, bits<6> opcode> {

// main memory - unmasked - 32
def Mainmem_U : FM_Unmasked_Mainmem_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # " $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Umem ADDRri:$addr))],
opcode>;

// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # "_scratchpad $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Uscratch ADDRri:$addr))],
opcode>;

// main memory - masked - 32
def Mainmem_M : FM_Masked_Mainmem_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # ".m $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Mmem ADDRri:$addr))],
opcode>;

// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins MEMri:$addr),
"load" # suffix # "_scratchpad.m $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Mscratch ADDRri:$addr))],
opcode>;
}

// Vector GATHER
multiclass FMGather_32<string suffix, Intrinsic op_Uscratch,
Intrinsic op_Mscratch, bits<6> opcode> {

// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins V16MEMri:$addr),
"loadg" # suffix # "_scratchpad $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Uscratch V16ADDRri:$addr))],
opcode>;
// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs VR512W:$dstsrc),
(ins V16MEMri:$addr),
"loadg" # suffix # "_scratchpad.m $dstsrc, $addr",
[(set v16i32:$dstsrc, (op_Mscratch V16ADDRri:$addr))],
opcode>;
}

// Vector STORE
multiclass FMStoreVector_32<string suffix, PatFrag op_Umem, PatFrag op_Uscratch,
Intrinsic op_Mmem, Intrinsic op_Mscratch, bits<6> opcode> {

// main memory - unmasked - 32
def Mainmem_U : FM_Unmasked_Mainmem_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # " $dstsrc, $addr",
[(op_Umem v16i32:$dstsrc, ADDRri:$addr)],
opcode>;
// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # "_scratchpad $dstsrc, $addr",
[(op_Uscratch v16i32:$dstsrc, ADDRri:$addr)],
opcode>;
// main memory - masked - 32
def Mainmem_M : FM_Masked_Mainmem_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # ".m $dstsrc, $addr",
[(op_Mmem ADDRri:$addr, v16i32:$dstsrc)],
opcode>;
// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, MEMri:$addr),
"store" # suffix # "_scratchpad.m $dstsrc, $addr",
[(op_Mscratch ADDRri:$addr, v16i32:$dstsrc)],
opcode>;
}

// Vector SCATTER
multiclass FMScatter_32<string suffix, Intrinsic op_Uscratch,
Intrinsic op_Mscratch, bits<6> opcode> {

// scratchpad memory - unmasked - 32
def Scratchpad_U : FM_Unmasked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, V16MEMri:$addr),
"stores" # suffix # "_scratchpad $dstsrc, $addr",
[(op_Uscratch V16ADDRri:$addr, v16i32:$dstsrc)],
opcode>;

// scratchpad memory - masked - 32
def Scratchpad_M : FM_Masked_Scratchpad_32<
(outs),
(ins VR512W:$dstsrc, V16MEMri:$addr),
"stores" # suffix # "_scratchpad.m $dstsrc, $addr",
[(op_Mscratch V16ADDRri:$addr, v16i32:$dstsrc)],
opcode>;
}

//===----------------------------------------------------------------------===//
// A set of multiclasses is used to handle Vector/Scalar
// Masked/Unmasked combinations
// MOVEI operations
//===----------------------------------------------------------------------===//

multiclass FMOVEI_ALL<string operator, bits<3> opcode> {
// SI
def SI : FMOVEI<
(outs GPR32:$dst),
(ins SIMM16OP:$imm),
operator # " $dst, $imm",
[],//[(set i32:$dst, simm16:$imm)],
opcode,
Fmt_S,
0>;

// VI unmasked
def VI_U : FMOVEI<
(outs VR512W:$dst),
(ins SIMM16OP:$imm),
operator # " $dst, $imm",
[],//[(set v16i32:$dst, (splat simm16:$imm))],
opcode,
Fmt_V,
0>;

let Constraints = "$dst = $oldvalue", Uses = [MR_REG] in {
// VI masked
def VI_M : FMOVEI<
(outs VR512W:$dst),
(ins SIMM16OP:$imm, VR512W:$oldvalue),
operator # ".m $dst, $imm",
[(set v16i32:$dst, (int_nuplus_vector_mixi32 (splat simm16:$imm), v16i32:$oldvalue))],
opcode,
Fmt_V,
1>;
}
}

//===----------------------------------------------------------------------===//
// Instruction class used to read/write special register through intrinics
// All these instructions are implemented using a move instruction
//===----------------------------------------------------------------------===//
let DecoderNamespace = "Read_SPR" in {
class READ_SPR<SpReg reg, string operator, Intrinsic read_intr> :
FR_OneOp_Unmasked_32<
(outs GPR32:$dst),
(ins),
operator # " $dst",
[(set i32:$dst, (read_intr))],
32,
Fmt_S,
Fmt_S>
{
bits<6> dst;

let Inst{29-24} = 32; // opcode: move
let Inst{23-18} = dst;
let Inst{17-12} = reg.Register;
let Inst{11-6} = 0;
}
}
let DecoderNamespace = "Write_SPR" in {
class WRITE_SPR<SpReg reg, string operator, Intrinsic read_intr> :
FR_OneOp_Unmasked_32<
(outs),
(ins GPR32:$src),
operator # " $src",
[(read_intr i32:$src)],
32,
Fmt_S,
Fmt_S>
{
bits<6> src;

let Inst{29-24} = 32; // opcode: move
let Inst{23-18} = reg.Register;
let Inst{17-12} = src;
let Inst{11-6} = 0;
}
}

//===----------------------------------------------------------------------===//
// Pseudo-instructions for alternate assembly syntax (never used by codegen).
// These are aliases that require C++ handling to convert to the target
// instruction, while InstAliases can be handled directly by tblgen.
//===----------------------------------------------------------------------===//
class AsmPseudoInst<dag outs, dag ins, string asm>
: InstNuPlus<outs, ins, asm, []> {
let isPseudo = 1;
}

class Pseudo<dag outs, dag ins, list<dag> pattern>
: InstNuPlus<outs, ins, "Pseudo", pattern>
{
let isCodeGenOnly = 1;
let isPseudo = 1;
let Inst{31-0} = 0;
}

multiclass AtomicBinary<SDNode OpNode>
{
def R : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, GPR32:$amt),
[(set i32:$dst, (OpNode GPR32:$ptr, GPR32:$amt))]>;

def I : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$ptr, SIMM9OP:$amt),
[(set i32:$dst, (OpNode GPR32:$ptr, simm9:$amt))]>;
}

</syntaxhighlight>

NuPlusInstrFormats.td

2019-06-21T14:42:50Z

Francesco: Francesco moved page NuPlusInstrFormats.td to NaplesPUInstrFormats.td

#REDIRECT [[NaplesPUInstrFormats.td]]

NaplesPUISelDAGToDAG.cpp

2019-06-21T14:42:20Z

Francesco: Francesco moved page NuPlusISelDAGToDAG.cpp to NaplesPUISelDAGToDAG.cpp

The NuPlusDAGToDAGISel class is used to transform target independent LLVM DAG nodes into platform dependent nodes.

<syntaxhighlight>
//===-- NuPlusISelDAGToDAG.cpp - A dag to dag inst selector for NuPlus ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This pass transforms target independent LLVM DAG nodes into platform
// dependent nodes that map, for the most part, directly to target instructions.
//
//===----------------------------------------------------------------------===//

#define DEBUG_TYPE "nuplus-isel"

#include "NuPlusTargetMachine.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;

namespace {
class NuPlusDAGToDAGISel : public SelectionDAGISel {
public:
explicit NuPlusDAGToDAGISel(NuPlusTargetMachine &tm) : SelectionDAGISel(tm) {}

void Select(SDNode *N) override;

bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
std::vector<SDValue> &OutOps) override;

bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);

StringRef getPassName() const override {
return "NuPlus DAG->DAG Pattern Instruction Selection";
}

#include "NuPlusGenDAGISel.inc"
};
} // end anonymous namespace

bool NuPlusDAGToDAGISel::SelectADDRri(SDValue Addr, SDValue &Base,
SDValue &Offset) {

if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
return true;
}

if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls.

if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
if (isInt<9>(CN->getSExtValue())) {
if (FrameIndexSDNode *FIN =
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
} else {
Base = Addr.getOperand(0);
}
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
MVT::i32);
return true;
}
}
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
return true;
}

void NuPlusDAGToDAGISel::Select(SDNode *N) {
SDLoc DL(N);
if (N->isMachineOpcode())
return; // Already selected.

SelectCode(N);
}

bool NuPlusDAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default:
return true;

case 'm': // memory
SelectADDRri(Op, Op0, Op1);
break;

}

OutOps.push_back(Op0);
OutOps.push_back(Op1);
return false;
}

FunctionPass *llvm::createNuPlusISelDag(NuPlusTargetMachine &TM) {
return new NuPlusDAGToDAGISel(TM);
}
</syntaxhighlight>

NuPlusISelDAGToDAG.cpp

2019-06-21T14:42:20Z

Francesco: Francesco moved page NuPlusISelDAGToDAG.cpp to NaplesPUISelDAGToDAG.cpp

#REDIRECT [[NaplesPUISelDAGToDAG.cpp]]

NaplesPUCallingConv.td

2019-06-21T14:41:40Z

Francesco: Francesco moved page NuPlusCallingConv.td to NaplesPUCallingConv.td

[[Category:Tablegen Files]]
This file describes the conventions to use when a function is called, such as how to pass the arguments and how to return the function results.

<syntaxhighlight>
//===-- NuPlusCallingConv.td - Calling Conventions NuPlus ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This describes the calling conventions for the NuPlus architectures.
//
//===----------------------------------------------------------------------===//

def CC_NuPlus32 : CallingConv<[

// i1, i8 and i16 integers are promoted to i32 by the caller.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,

CCIfType<[v16i8, v16i16], CCPromoteToType<v16i32>>,
CCIfType<[v8i8, v8i16, v8i32], CCPromoteToType<v8i64>>,

// i32 f32 arguments get passed in integer registers if there is space.
CCIfNotVarArg<CCIfType<[i32, f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>>,

// Vector arguments can be passed in their own registers, as above
CCIfNotVarArg<CCIfType<[v16i32, v16f32], CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>>,

// Stick remaining registers onto stack, aligned by size
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
CCIfType<[v16i32, v16f32], CCAssignToStack<64, 64>>
]>;

def RetCC_NuPlus32 : CallingConv<[
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,

CCIfType<[i32, f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5]>>,

CCIfType<[v16i8, v16i16], CCPromoteToType<v16i32>>,

CCIfType<[v16i32, v16f32], CCAssignToReg<[V0, V1, V2, V3, V4, V5]>>
]>;

//Callee only needs to save the callee-save registers that are used in the body of its subroutine.
def NuPlusCSR : CalleeSavedRegs<(add (sequence "S%u", 50, 57), MR_REG, FP_REG, RA_REG,
(sequence "V%u", 56, 63))>;
</syntaxhighlight>

NuPlusCallingConv.td

2019-06-21T14:41:40Z

Francesco: Francesco moved page NuPlusCallingConv.td to NaplesPUCallingConv.td

#REDIRECT [[NaplesPUCallingConv.td]]

NaplesPURegisterInfo.td

2019-06-21T14:41:12Z

Francesco: Francesco moved page NuPlusRegisterInfo.td to NaplesPURegisterInfo.td

[[Category:Tablegen Files]]
The NuPlusRegisterInfo.td is used to define the nu+ hw registers and the nu+ register classes.

<syntaxhighlight lang="c" line='line'>
//===-- NuPlusRegisterInfo.td - NuPlus Register defs ---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Declarations that describe the NuPlus register file
//===----------------------------------------------------------------------===//

let Namespace = "NuPlus" in {
def sub_even : SubRegIndex<32>;
def sub_odd : SubRegIndex<32, 32>;
}

class NuPlusReg<bits<16> Enc, string n> : Register<n> {
let HWEncoding = Enc;
let Namespace = "NuPlus";
}

class NuPlusRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
: RegisterWithSubRegs<n, subregs> {
let HWEncoding = Enc;
let Namespace = "NuPlus";
}

// NuPlus 32-bit registers
class NuPlusGPRReg<bits<16> Enc, string n> : NuPlusReg<Enc, n>;

//===----------------------------------------------------------------------===//
// Registers
//===----------------------------------------------------------------------===//

// General Purpose scalar registers
foreach i = 0-57 in {
def S#i : NuPlusGPRReg<i, "s"#i>, DwarfRegNum<[i]>;
}

//trap register
def TR_REG : NuPlusGPRReg<58, "tr">, DwarfRegNum<[58]>;
//mask register
def MR_REG : NuPlusGPRReg<59, "rm">, DwarfRegNum<[59]>;
//frame pointer
def FP_REG : NuPlusGPRReg<60, "fp">, DwarfRegNum<[60]>;
//stack pointer
def SP_REG : NuPlusGPRReg<61, "sp">, DwarfRegNum<[61]>;
//return address
def RA_REG : NuPlusGPRReg<62, "ra">, DwarfRegNum<[62]>;
//PC
def PC_REG : NuPlusGPRReg<63, "pc">, DwarfRegNum<[63]>;

// General Purpose vectorial registers
foreach i = 0-63 in {
def V#i : NuPlusGPRReg<i, "v"#i>, DwarfRegNum<[!add(i, 64)]>;
}

//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//

// This register class should not be used to hold i64/f64 values, use the GPR64
// register class for that. The i64/f64 type is included here to allow i64/f64
// patterns using the instructions.
def GPR32 : RegisterClass<"NuPlus", [i32, f32], 32, (add (sequence "S%u", 0, 57),
TR_REG, MR_REG, FP_REG, SP_REG, RA_REG, PC_REG)>

def VR512W : RegisterClass<"NuPlus", [v16i32, v16f32, v16i8, v16i16], 512, (sequence "V%u", 0, 63)>;
</syntaxhighlight>

NuPlusRegisterInfo.td

2019-06-21T14:41:12Z

Francesco: Francesco moved page NuPlusRegisterInfo.td to NaplesPURegisterInfo.td

#REDIRECT [[NaplesPURegisterInfo.td]]

NuPlus.td

2019-06-21T14:39:58Z

Francesco: Francesco moved page NuPlus.td to NaplesPU.td

#REDIRECT [[NaplesPU.td]]

NaplesPU.td

2019-06-21T14:39:57Z

Francesco: Francesco moved page NuPlus.td to NaplesPU.td

[[Category:Tablegen Files]]
The NuPlus.td file contains the definition of the Target class '''NuPlus''' (defined in "compiler/include/llvm/Target/Target.td"). The file also contains the definition of the '''NuPlusInstrInfo''', '''NuPlusAsmParser''' and '''NuPlusAsmWriter''' required by the '''Target''' class. In addition, we avoid using instruction itineraries for scheduling. Itineraries are details reservation tables for each instruction class.

<syntaxhighlight lang="c" line='line'>
//===-- NuPlus.td - Describe the NuPlus Target Machine -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//

include "NuPlusRegisterInfo.td"
include "NuPlusCallingConv.td"
include "NuPlusInstrInfo.td"

def NuPlusInstrInfo : InstrInfo;

def NuPlusAsmParser : AsmParser {
bit ShouldEmitMatchRegisterName = 1;
}

//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//

def NuPlusAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
bit isMCAsmWriter = 1;
}

def : Processor<"nuplus", NoItineraries, []>;

def NuPlus : Target {
// Pull in Instruction Info:
let InstructionSet = NuPlusInstrInfo;
let AssemblyParsers = [NuPlusAsmParser];
let AssemblyWriters = [NuPlusAsmWriter];
}

</syntaxhighlight>

NaplesPU LLVM Documentation

2019-06-21T14:37:29Z

Francesco: Francesco moved page Nu+ LLVM Documentation to NaplesPU LLVM Documentation

The main task of the backend is to generate NPU assembly code from the LLVM IR obtained by the Clang frontend. It also handles object representation of classes needed to create the assembler and the disassembler.
The NPU backend is contained in the '''NaplesPU''' folder under "compiler/lib/Target" directory. It contains several files, each implementing a specific class of the LLVM Framework.

An LLVM backend is constructed on two types of file, C++ and TableGen source files. Refer to section [[#TableGen | TableGen]] to get a detailed explanation of the latters.

== Required reading ==
Before working on LLVM, you should be familiar with some things. In particular:
# [https://en.wikipedia.org/wiki/Basic_block '''Basic Blocks''']
# [https://en.wikipedia.org/wiki/Static_single_assignment_form '''SSA''' (Static Single Assignment) form]
# [https://en.wikipedia.org/wiki/Abstract_syntax_tree '''AST''' (Abstract Syntax tree)]
# [https://en.wikipedia.org/wiki/Directed_acyclic_graph '''DAG''' Direct Acyclic Graph].

In addition to general aspects about compilers, it is recommended to review the following topics:
#[http://www.aosabook.org/en/llvm.html '''LLVM architecture''']
#[http://llvm.org/docs/LangRef.html '''LLVM Intermediate Representation''']

See the following textbook for other information [http://books.tarsoit.com/Getting%20Started%20with%20LLVM%20Core%20Libraries.pdf Getting Started with LLVM Core Libraries] and [https://github.com/iBreaker/book/blob/master/LLVM%20Cookbook.pdf LLVM Cookbook].

See also [https://eli.thegreenplace.net/2012/11/24/life-of-an-instruction-in-llvm this article] to get an overview of the main CodeGenerator phases.

== TableGen ==

TableGen is a record-oriented language used to describe the target-specific information. It is written by the LLVM team in order to simplify the back-end development and to avoid potential code redundancy. For example, by using TableGen, if some feature of the target-specific register file changes, you do not need to modify different files wherever the register appears but you need only to modify the ''.td'' file that contains its definition. Actually, the TableGen is used to define instruction formats, instructions, registers, pattern-matching DAGs, instruction selection matching order, calling conventions, and target platform properties.

For other information, check the [http://llvm.org/docs/TableGen/index.html TableGen Documentation]

== Backend Description ==

This section shows how is implemented the backend support for NPU within LLVM.

=== Target Definition ===

The target-specific information is explained in TableGen files. The custom target is defined by creating a new [[NaplesPU.td]] file, in which the target itself is described. This file contains the implementation of the target-independent interfaces provided by ''Target.td''. Implementations are done by using the class inheritance mechanism.

The code below is the ''Target'' class definition that should be implemented in [[NaplesPU.td]].

<syntaxhighlight>
class Target {
InstrInfo InstructionSet;
list<AsmParser> AssemblyParsers = [DefaultAsmParser];
list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
}
</syntaxhighlight>

This file should also include the other defined ''.td'' target-related files. The target definition is done as follows:

<code>def : Processor<"naplespu", NoItineraries, []>;</code>

where ''Processor'' is a class defined in ''Target.td'':
<code>class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f></code>

where:
* ''n'' is the chipset name, used in the command line option ''-mcpu'' to determine the appropriate chip.
* ''p'' is the processor itinerary, as described in the theoretical description of the LLVM ''instruction scheduling'' phase. ''NoItinerary'' means that no itinerary is defined.
* ''f'' is a list of target features.

=== Registers Definition ===
The target-specific registers are defined in [[NaplesPURegisterInfo.td]]. LLVM provides two ways to define a register, both of them declared in ''Target.td''. The first one is used to define a simple scalar register and follows the declaration below:

<code>class Register<string n, list<string> altNames = []></code>

where ''n'' is the register name, while ''altNames'' is a list of register alternative names.

The second method to define a register is to inherit from the class declared below:

<code>class RegisterWithSubRegs<string n, list<Register> subregs> </code>

This second way is used when it is required to define a register that is a collection of ''n'' sub-registers.
There is also a third way to define registers. It consists of defining a ''super-register'', that is a pseudo-register resulting of the combination of other sub-registers. It is useful when there is no architectural support for larger registers:

<code>class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs></code>

For example, the following code is the declaration of the register class:

<code>class NaplesPUGPRReg<string n> : Register <n>;</code>

At this point, registers can be instantiated as follows:

<syntaxhighlight>
foreach i = 0-57 in {
def S#i : NaplesPUGPRReg<"s"#i>, DwarfRegNum<[i]>;
}
...
def SP_REG : NaplesPUGPRReg<"sp">, DwarfRegNum<[61]>; //stack pointer
...
foreach i = 0-63 in {
def V#i : NaplesPUGPRReg<"v"#i>, DwarfRegNum<[!add(i, 64)]>;
}
</syntaxhighlight>

The instantiation reflects the custom target hardware architecture, with a set of scalar registers and a set of vectorial ones.
Each register inherits also from the''DwarfRegNum'' assigning to it an incremental number. This is useful for the internal identification of registers, consistent with the ''DWARF'' standard.

Now that registers are defined they must belong to classes in order to define the allocation of them.

LLVM provides the ''RegisterClass'' defined as below:

<code>class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, dag regList></code>

in which:

* ''namespace'' is the namespace associate to it;
* ''regTypes'' is a list of ''ValueType'' values indicating the types of variables that can be allocated into them;
* ''alignment'' is the alignment associated to the registers in the ''RegisterClass'';
* ''regList'' is the list of registers that belong to the class. Since the parameter type is ''dag'', TableGen provides operands to define a set of registers in terms of a set of operators.

For example, to match our target features it is necessary to define two classes:
* GPR32, that is the abstraction of 32-bit wide scalar registers;
* VR512W, that are the abstraction of 512-bit wide vectorial registers;

<syntaxhighlight>
def GPR32 : RegisterClass<"NaplesPU", [i32, f32, i64, f64], 32, (add (sequence "S%u", 0, 57),
TR_REG, MR_REG, FP_REG, SP_REG, RA_REG, PC_REG)>;
def VR512W : RegisterClass<"NaplesPU", [v16i32, v16f32, v16i8, v16i16], 512, (sequence "V%u", 0, 63)>;
</syntaxhighlight>

=== Calling Convention ===

This section shows how to define the ''calling convention'', that is how ''parameters'' are passed to sub-functions, and how the ''return value'' is sent back to the caller.

The calling convention is defined in the [[NaplesPUCallingConv.td]] by using the classes defined in the ''TargetCallingConv.td'' file.

In our purposes, it's required to define the calling convention in terms of the registers used to pass the arguments to the callee.
LLVM provides the ''CallingConv'' class defined below:

<code>class CallingConv<list<CCAction> actions></code>

This class requires a list of ''CCAction''. ''TargetCallingConv.td'' contains a set of ''CCAction'' derived classes that must be used to define the sub-function calling behaviour.

The calling convention for the custom target device is defined by using the first ''eight'' registers, and then the stack for the remaining parameters. It means that for 32-bit variables, they are passed to the callee by using the registers Si, where i = 0..7.
The same schema is adopted for vectorial variables.

The calling convention should also take care of the passing of type that is not natively supported by the target. In this case, the solution adopted is the type promotion. The mechanism is simple: it consists of promoting the unsupported type to a supported one. It can be easily implemented by only using the ''CCAction'' classes provided by LLVM.
By using the just described approach, ''i1, i8, i16'' are promoted to ''i32'' while ''v16i8, v16i16'' are promoted to ''v16i32''.

<syntaxhighlight>
def CC_NaplesPU : CallingConv<[
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
CCIfType<[v16i8, v16i16], CCPromoteToType<v16i32>>,
CCIfNotVarArg<CCIfType<[i32, f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>>,
CCIfNotVarArg<CCIfType<[v16i32, v16f32], CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>>,
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
CCIfType<[v16i32, v16f32], CCAssignToStack<64, 64>>
]>;
</syntaxhighlight>

The calling convention for NPU in terms of results returning mechanism is realized by passing them in the first six registers.

It could be also possible that the return type does not correspond to any native target type. The solution is ''promoting''.

<syntaxhighlight>
def RetCC_NaplesPU32 : CallingConv<[
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
CCIfType<[i32, f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5]>>>
</syntaxhighlight>

LLVM also provides a mechanism to define the registers that the callee must save before starting the function execution. The mechanism consists in defining an instance of the class ''CalleeSavedRegs'':

<code>class CalleeSavedRegs<dag saves></code>

where ''saves'' is the list of registers to be saved.

For example, in NPU, the callee saved registers are defined as follows:

<code>def NaplesPUCSR : CalleeSavedRegs<(add (sequence "S%u", 50, 57), MR_REG, FP_REG, RA_REG, (sequence "V%u", 56, 63))>;</code>

=== ISA Support ===

In order to define the LLVM support for NPU, the next step is to handle the target-specific code generation by implementing its ''ISA'' (Instruction Set Architecture) in LLVM.
In order to describe it, TableGen provides the class ''Instruction'' located in ''Target.td''.

<syntaxhighlight>
class Instruction {
string Namespace = "";
dag OutOperandList;
dag InOperandList;
string AsmString = "";
list<dag> Pattern;
list<Register> Uses = [];
list<Register> Defs = [];
list<Predicate> Predicates = [];
int Size = 0;
bit isReturn = 0;
bit isBranch = 0;
bit isPseudo = 0;
bit isCodeGenOnly = 0;
bit isAsmParserOnly = 0;
...
}
</syntaxhighlight>

As it is clear, the ''Instruction'' class provides a lot of member variable to describe an instruction. The following are a subset that is used for our purposes:

* ''OutOperandList'' is the set of output operands of the instruction, defined as of ''dag'' type.
* ''InOperandList'' is the set of input operands of the instruction, defined as of ''dag'' type.
* ''AsmString'' is the''.s'' format to print the instruction with.
* ''isReturn'' defines the instruction as a ''return'' one.
* ''isBranch'' defines the instruction as a ''branch'' one, that is, it breaks the sequential control flow.
* ''isPseudo'' defines the instruction as a ''pseudo'' one, or rather an instruction for which there is not a corresponding machine instruction.
* ''isCodeGenOnly'', ''isAsmParserOnly'' and ''usesCustomInserter'' are also defining a pseudo-instruction, but with different behaviour. The first field is describing a pseudo-instruction that is used for CodeGen modeling purposes while the second one is describing a pseudo-instruction used by the assembler parser. The third one tells that the pseudo-instruction needs to be manually lowered to a machine instruction.
* ''Uses'' and ''Defs'' are lists of registers that are respectively read and written by the instruction.
* ''Predicates'' are logical expressions that must be checked in the Instruction Selection phase.
* ''Pattern'' is a list of ''dag'', each of them explains a DAG Pattern for the instruction used by the instruction selector to turn a set of ''SelectionDAG}'' nodes in the corresponding target-specific instruction.

In order to handle the target platform ISA complexity it has been adapted a hierarchical schema of classes, each one represents a specific instruction format.

First of all it is defined a generic format for the target-specific instruction:

<syntaxhighlight>
class InstNaplesPU<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
field bits<32> Inst;
let Namespace = "MyTarget";
let Size = 4;
dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
}
</syntaxhighlight>

All instruction classes are inherited by the one above, specifying what the instruction bits are representing. Since the target supports different types of instruction format, for each of them is defined as a different class. Each class is then defined in terms of other sub-classes. For example, it may be useful to analyze the ''R'' format, that is the instruction format used to handle logical and arithmetic operations and memory operations.
By analyzing the instruction type it may be useful to distinguish among different sub-types, by structuring a hierarchy.

[[File:Formats_hierarchy.jpg|This picture shows how the classes are inherited from the FR class.]]

In this way, we shall define a set of classes implementing the hierarchy exposed, from the root, that represents the most generic R-type instruction, to leaves. Since the instruction format requires a set of ''FMT'' bits, it is also necessary to define a class to handle them:
<syntaxhighlight>
class Fmt<bit val> {
bit Value = val;
}
</syntaxhighlight>

The root class is defined as the most general class of the hierarchy. For this reason, the second source operand is not defined. The derived class, implementing the two-operand R-type instruction, will properly set the related field.

<syntaxhighlight>
class FR<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: InstNaplesPU<outs, ins, asmstr, pattern> {
bits <6> dst;
bits <6> src0;
let Inst{31-30} = 0;
let Inst{29-24} = opcode;
let Inst{23-18} = dst;
let Inst{17-12} = src0;
let Inst{5} = 0; //unused
let Inst{4} = 0; //No 64-bit support
let Inst{3} = fmt2.Value;
let Inst{2} = fmt1.Value;
let Inst{1} = fmt0.Value;
let Inst{0} = 1;
let Uses=[MR_REG];
}

class FR_TwoOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR<outs, ins, asmstr, pattern, opcode, fmt2, fmt1, fmt0> {
bits <6> src1;
let Inst{11-6} = src1;

}

class FR_OneOp<dag outs, dag ins, string asmstr, list<dag> pattern, bits<6> opcode, Fmt fmt2, Fmt fmt1, Fmt fmt0>
: FR_TwoOp<outs, ins, asmstr, pattern, opcode, fmt2, fmt1, fmt0> {
let Inst{11-6} = 0;
}
</syntaxhighlight>

The code above is showing the implementation of the classes hierarchy illustrated above.
All the other instruction format are implementing by using the same method.

However, the class definition method is not a flexible way to explain the commonalities among more than two definition instances. As a solution, LLVM provides the ''multiclass'' construct. For example, if an arithmetic instruction is designed to work both with an immediate value or two registers, the class construct forces to have implementation as described below.

<syntaxhighlight>
class rrinst<int opc, string asmstr>
: inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
(ops GPR:$dst, GPR:$src1, GPR:$src2)>;
class riinst<int opc, string asmstr>
: inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
(ops GPR:$dst, GPR:$src1, Imm:$src2)>;
def ADD_rr : rrinst<0b111, "add">;
def ADD_ri : riinst<0b111, "add">;
...
</syntaxhighlight>

The usage of the class construct in this context is quietly unfeasible. Differently, below is showed how clean is the approach using the ''multiclass'' construct.

<syntaxhighlight>
multiclass ri_inst<int opc, string asmstr> {
def _rr : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
(ops GPR:$dst, GPR:$src1, GPR:$src2)>;
def _ri : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
(ops GPR:$dst, GPR:$src1, Imm:$src2)>;
}
defm ADD : ri_inst<0b111, "add">;
...
</syntaxhighlight>

The ''multiclass'' construct is used to handle different register types for arithmetic operations. Therefore, despite defining several classes, one for each combination of scalar and vectorial registers as source operands, the usage of the ''multiclass'' construct is the best solution to do it.

<syntaxhighlight>
multiclass FArithInt_TwoOp<string operator, SDNode OpNode, bits<6> opcode> {
def SSS_32 : FR_TwoOp<
(outs GPR32:$dst),
(ins GPR32:$src0, GPR32:$src1),
operator # "_i32 $dst, $src0, $src1",
[(set i32:$dst, (OpNode i32:$src0, i32:$src1))],
opcode,
Fmt_S,
Fmt_S,
Fmt_S>;
</syntaxhighlight>

=== Pattern Recognition ===

The ''Instruction Selection'' phase tries to substitute the IR instruction with the target-specific one. This pass is structured in two ways implemented in ''Select()'' method of the ''SelectionDAGISel'' class: the first way tries to find an instruction matching by looking at the target description provided by the compiled TableGen files, while the second way is looking to a custom code matching defined by the user.

Consequently, it is useful to define instruction patterns in order to help the ''Select'' method to find a proper match. TableGen defines a set of classes that are used to declare a pattern.

For example, an important concept implemented is the ''Pattern Fragment'', that is a reusable chunk of DAG that matches specific nodes. LLVM provides few implementation of the mentioned class, starting from the ''PatFrag'', that is the most general class, to ''OutPatFrag'', ''PatLeaf'' and ''ImmLeaf'' inherited from the first one.

The''PatFrag'' definition is showed below:

<code>class PatFrag<dag ops, dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator</code>

where:

* ''ops'' represents the input operands;
* ''frag'' is the fragment to be matched;
* ''pred'' is the predicate to be satisfied in order to apply the transformation;
* ''xform'' is the transformation to be applied if all the previous points are fulfilled.

In NaplesPU, the ''PatFrag'' class is used to handle the ''store'' operations, in terms of the address space they refer to. In our purposes, it is required to define a store operation in the global memory if and only if it is satisfied with a condition on the address space identification number. Otherwise, the memory operation refers to the ''scratchpad'' address space.

<syntaxhighlight>
def MemStore : PatFrag<(ops node:$val, node:$ptr),
(store node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() != 77)
return !cast<StoreSDNode>(N)->isTruncatingStore();
else
return false;}]>;
def ScratchpadStore : PatFrag<(ops node:$val, node:$ptr),
(store node:$val, node:$ptr), [{
if(cast<StoreSDNode>(N)->getAddressSpace() == 77)
return !cast<StoreSDNode>(N)->isTruncatingStore();
else
return false;}]>;
</syntaxhighlight>

''PatLeaf'' is the a ''PatFrag'' sub-class, deprived of the transformation and the pattern parameters, used, for example, to handle the ''immediate'' values transformation.

<syntaxhighlight>
def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
def simm9 : PatLeaf<(imm), [{ return isInt<9>(N->getSExtValue()); }]>;
</syntaxhighlight>

The pattern exposed is used to recognise if the immediate is 9-bit wide or 16-bit wide.
LLVM also provides a class that is used to define more complex patterns than the ones explained above. It is typically used to handle the ''addressing modes''.
The described behaviour is implemented in the class ''ComplexPattern'':

<code>class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = [], list<SDNodeProperty> props = []> </code>

where:
* ''ty'' is the type associated to the pattern;
* ''numops'' is the number of operands returned by the function;
* ''n'' is the name of the function;
* ''roots'' is the list of possible \textit{root nodes} of the sub-DAG to match;
* ''props'' is a list of possible predicates to match.

As mentioned above, this pattern is usually used to handle the addressing modes. In our purpose, the pattern is used to evaluate the address as ''base plus offset''. For this reason, it is necessary to define a proper function in the ''Select()'' method [[NaplesPUISelDAGToDAG.cpp]] file.

The following line shows how to define a ''ComplexPattern'' instance.

<code>def ADDRri:ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;</code>

The pattern above calls the method ''SelectADDRri'' defined in the [[NaplesPUISelDAGToDAG.cpp]] when an SDNode is of ''iPTR'' type.

=== Instructions definition ===
This section describes how to use the formats defined in [[NaplesPUInstrFormats.td]] to instantiate the target-specific instructions.
Because of the instruction formats definition described before, the target-specific ISA can be realized by simply instantiating the formats themselves.

For instance, the ''ADD'' instruction is of the ''arithmetic'' format, that is implemented by using the ''multiclass'' construct. As a consequence, the instantiation is:

<code> defm ADD:FArithInt_TwoOp<"add", add, 4></code>

The other arithmetic instructions are implemented in a similar way as above.
Thanks to the ''multiclass'' construct a single definition instantiates scalar and vector variants of the ''ADD'' instruction.

Instruction definition is located in [[NaplesPUInstrInfo.td]].

There are some cases in which the TableGen generated outputs are not enough to produce a legalized DAG composed of only machine instruction nodes. In these cases could be useful to define a pattern that helps the instruction selection algorithm to find a match. Beyond the ''PatFrag'' class, LLVM provides an explicit way to force a pattern matching through the class ''Pat'', defined as follows:

<code> class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;</code>

For instance, consider the frontend intrinsic ''int_npu_vector_mix32''. It is converted in a target-specific node through the ''Pat'' class, as explained below.

<code> def : Pat<(int_npu_vector_mixf32 v16f32:$src0, v16f32:$oldvalue), (MOVE_VV_M_32 v16f32:$src0, v16f32:$oldvalue)>; } </code>

As a result of the pattern application, the considered node is transformed into ''MOVE_VV_M_32'' that is a target-specific node.

Even though the use of ''Pat'' s an easy-to-apply solution to help the instruction selector, its power is limited to simple substitutions.
More complex behaviors have to be managed manually in the ''Lowering'' Pass.

=== Instruction Selection Lowering ===

Because the TableGen description is not enough to have a full substitution of target-dependent nodes, LLVM provides a ''C++'' file to implement the lowering pass, that [[NaplesPUISelLowering.cpp]].
In our purpose, the lowering mainly concerns the ''pseudo-instructions'' defined in [[NaplesPUInstrInfo.td]]. Recall that a pseudo-instruction is a special instruction that does not map to any machine code. For example, it is helpful to analyze how is managed the ''load'' operation associated to a 32-bit immediate value.
The 32-bit instruction format allows the ''move'' operation for an immediate operand that is at most 16-bit wide. To handle wider immediate operands it is necessary to find a solution.
By looking at [[NaplesPUInstrInfo.td]], the mentioned operation, named ''LoadI32'', is defined as a pseudo-instruction with ''usesCustomInserter'' bit set, as showed below.

<syntaxhighlight>
let usesCustomInserter = 1 in {
def LoadI32 : Pseudo<
(outs GPR32:$dst),
(ins GPR32:$val),
[(set i32:$dst, (i32 imm:$val))]>;
...
</syntaxhighlight>

The LLVM APIs are designed to deal with DAG nodes. To handle the ''Load32I'' operation, ''MOVEIH'' and ''MOVEIL'' instructions are used. For this reason, the 32-bit value is split into two sub-values, each one of 16-bit wide that can be used to build the machine instruction nodes.

<syntaxhighlight>
MachineBasicBlock *
NaplesPUTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) const {
switch (MI.getOpcode()) {
case NaplesPU::LoadI32:
return EmitLoadI32(&MI, BB);
...
</syntaxhighlight>

The ''LoadI32'' is split into two machine instruction, one that uses the MOVEIH instruction and the other that uses the MOVEIL instruction, as the code below explains.

<syntaxhighlight>
MachineBasicBlock* EmitLoadI32(...) const {
DebugLoc DL = MI->getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
int64_t ImmOp = MI->getOperand(1).getImm();
if((ImmOp & 0xFFFF0000) != 0)
InsertLoad32Immediate(...);
...
MI->eraseFromParent();
return BB;
}

void InsertLoad32Immediate (...) {
BuildMI(*BB, *MI, *DL, TII->get(NaplesPU::MOVEIHSI))
.addReg(DestReg, RegState::Define)
.addImm(((Immediate >> 16) & 0xFFFF));
BuildMI(*BB, *MI, *DL, TII->get(NaplesPU::MOVEILSI))
.addReg(DestReg)
.addImm((Immediate & 0xFFFF));
}
</syntaxhighlight>

=== Frame Lowering ===
This section focuses on the definition of information about the stack frame layout on the target.
For this purpose, LLVM provides a target-independent interface, defined in ''TargetFrameLowering'', that has to be implemented for the target platform. It holds several pieces of information such as the direction of stack growth, the known stack alignment on entry to each function, and the offset to the local area.

The custom platform is provided of a down-growing stack, 64-bit aligned. The specific implementation of the interface ''TargetFrameLowering'' is defined in the file [[NaplesPUFrameLowering.cpp]], and it includes the development of the following functions:

* ''emitPrologue'' and ''emitEpilogue'', used to add the prologue and the epilogue code to a function, in terms of stack managing.
* ''eliminateCallFramePseudoInstr'' is the function devolved to replace the IR Call-Frame composed by pseudo-instructions with the target-specific one.
* ''hasReservedCallFrame'' is a boolean function that is used to check whether the prologue inserter should reserve stack space or not.
* ''hasFP'' is a boolean function that returns true if the specified function should have a dedicated frame pointer register.
* ''determineCalleeSaves'' determines which of ''CalleeSavedRegs'' should be actually saved.

=== Code Emission Support ===
The code emission phase starts with the ''AsmPrinter'' pass. The core of this pass is the ''EmitInstruction'' function, that requires an ''MachineInstr'' object as input and transforms it in a ''MCInst'' instance. This transformation is done by using the ''Lower'' method, defined in [[NaplesPUMCInstLower.cpp]]. The MCInst instances generated are sent to the ''MCStreamer'', that can switch between two different ways: the generation of the binary target-specific code or the generation of the assembly code by using the ''MCObjectStreamer'' object in the first case and the ''MCAsmStreamer'' one in the latter.
The target-specific behavior is implemented in the class [[NaplesPUInstPrinter.cpp]] to handle the assembly code generation and in the class [[NaplesPUMCCodeEmitter.cpp]] to handle the binary code generation.

Nu+ LLVM Documentation

2019-06-21T14:37:29Z

Francesco: Francesco moved page Nu+ LLVM Documentation to NaplesPU LLVM Documentation

#REDIRECT [[NaplesPU LLVM Documentation]]

NaplesPU LLVM Documentation

2019-06-21T14:37:13Z

Francesco: