Difference between revisions of "System deployment"
From NaplesPU Documentation
| Line 1: | Line 1: | ||
TODO: descrizione uart_router, memory_controller, con riferimento a template nexys4ddr, (comandi, console) e memoria, disegno/schema, interazione con host, loading memoria, avvio kernel | TODO: descrizione uart_router, memory_controller, con riferimento a template nexys4ddr, (comandi, console) e memoria, disegno/schema, interazione con host, loading memoria, avvio kernel | ||
| − | The Single core version | + | The [[Single core version|SC_System]] has been deployed on a Nexys4DDR FPGA board, modules involved are located into ''boards/nexys4ddr'' and ''src/deploy/'' folders. The design interconnects the board DDR memory and the UART to respectively the Memory and Item interfaces. The figure below shows a schematic block of the top module: |
| + | |||
[[File:Nexys4DDR.jpg|900px]] | [[File:Nexys4DDR.jpg|900px]] | ||
Revision as of 18:23, 14 May 2019
TODO: descrizione uart_router, memory_controller, con riferimento a template nexys4ddr, (comandi, console) e memoria, disegno/schema, interazione con host, loading memoria, avvio kernel
The SC_System has been deployed on a Nexys4DDR FPGA board, modules involved are located into boards/nexys4ddr and src/deploy/ folders. The design interconnects the board DDR memory and the UART to respectively the Memory and Item interfaces. The figure below shows a schematic block of the top module:
Memory Controller
da AXI a DDR
Host interaction
Uart controller e traduzione in items per nu+ (da uart_router)
Console commands
uart_loader.py
