User contributions
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- 15:15, 28 June 2019 (diff | hist) . . (+405) . . ISA (→C type instructions)
- 15:13, 28 June 2019 (diff | hist) . . (-18) . . ISA (→R type instructions)
- 15:13, 28 June 2019 (diff | hist) . . (-18) . . ISA (→I type instructions)
- 15:12, 28 June 2019 (diff | hist) . . (+6) . . ISA (→MOVEI type instructions)
- 15:12, 28 June 2019 (diff | hist) . . (0) . . N File:MOVEI format.png (current)
- 15:12, 28 June 2019 (diff | hist) . . (-10) . . ISA (→MOVEI type instructions)
- 15:11, 28 June 2019 (diff | hist) . . (+518) . . ISA (→MOVEI type instructions)
- 15:05, 28 June 2019 (diff | hist) . . (+6) . . ISA (→I type instructions)
- 15:04, 28 June 2019 (diff | hist) . . (0) . . N File:I instr.png (current)
- 15:04, 28 June 2019 (diff | hist) . . (+639) . . ISA (→I type instructions)
- 14:59, 28 June 2019 (diff | hist) . . (+854) . . ISA (→R type instructions)
- 14:57, 28 June 2019 (diff | hist) . . (+6) . . ISA (→R type instructions)
- 14:57, 28 June 2019 (diff | hist) . . (0) . . N File:RR format.png (current)
- 14:57, 28 June 2019 (diff | hist) . . (+5) . . ISA (→R type instructions)
- 14:56, 28 June 2019 (diff | hist) . . (+91) . . ISA (→R type instructions)
- 14:53, 28 June 2019 (diff | hist) . . (+641) . . ISA
- 14:52, 28 June 2019 (diff | hist) . . (+1) . . Core (→Control registers) (current)
- 15:44, 25 June 2019 (diff | hist) . . (+6) . . Coherence Injection (→Understanding the Testbench) (current)
- 15:43, 25 June 2019 (diff | hist) . . (0) . . N File:Tb coherence injection schema new.jpg (current)
- 15:43, 25 June 2019 (diff | hist) . . (-2) . . Coherence Injection (→Understanding the Testbench)
- 15:43, 25 June 2019 (diff | hist) . . (0) . . File:Tb coherence injection schema.jpg (Mirko uploaded a new version of File:Tb coherence injection schema.jpg) (current)
- 15:34, 25 June 2019 (diff | hist) . . (+13) . . SC Synch (current)
- 15:33, 25 June 2019 (diff | hist) . . (-34) . . SC Synch
- 15:32, 25 June 2019 (diff | hist) . . (-45) . . SC Logger
- 15:31, 25 June 2019 (diff | hist) . . (-35) . . SC Item (current)
- 15:28, 25 June 2019 (diff | hist) . . (-339) . . SC Item
- 15:24, 25 June 2019 (diff | hist) . . (+235) . . SC Item
- 15:21, 25 June 2019 (diff | hist) . . (+312) . . SC Logger
- 15:18, 25 June 2019 (diff | hist) . . (+41) . . SC Item (→Querying Logger)
- 15:17, 25 June 2019 (diff | hist) . . (+13) . . SC System (current)
- 15:16, 25 June 2019 (diff | hist) . . (+104) . . SC System
- 15:13, 25 June 2019 (diff | hist) . . (+4) . . Network interface (→Core to network module)
- 15:11, 25 June 2019 (diff | hist) . . (-13) . . Network interface (→Control unit)
- 14:39, 25 June 2019 (diff | hist) . . (+6) . . Programming Model (→Execution Model Matching)
- 14:39, 25 June 2019 (diff | hist) . . (0) . . N File:Execution model new.png (current)
- 14:38, 25 June 2019 (diff | hist) . . (-1) . . Programming Model (→Execution Model Matching)
- 14:36, 25 June 2019 (diff | hist) . . (0) . . Programming Model (→Memory Model Matching)
- 14:36, 25 June 2019 (diff | hist) . . (0) . . File:Memory mod new.png (Mirko uploaded a new version of File:Memory mod new.png) (current)
- 14:35, 25 June 2019 (diff | hist) . . (-1) . . Programming Model (→Memory Model Matching)
- 14:35, 25 June 2019 (diff | hist) . . (+1) . . Programming Model (→Memory Model Matching)
- 14:34, 25 June 2019 (diff | hist) . . (+6) . . Programming Model (→Memory Model Matching)
- 14:34, 25 June 2019 (diff | hist) . . (0) . . N File:Memory mod new.png
- 14:34, 25 June 2019 (diff | hist) . . (-2) . . Programming Model (→Memory Model Matching)
- 14:33, 25 June 2019 (diff | hist) . . (+6) . . Programming Model (→OpenCL support for NaplesPU)
- 14:33, 25 June 2019 (diff | hist) . . (0) . . N File:Plat model new.png (current)
- 14:32, 25 June 2019 (diff | hist) . . (-2) . . Programming Model (→OpenCL support for NaplesPU)
- 14:32, 25 June 2019 (diff | hist) . . (0) . . File:Plat model.png (Mirko uploaded a new version of File:Plat model.png) (current)
- 14:09, 25 June 2019 (diff | hist) . . (-22) . . Network (→General architecture) (current)
- 13:54, 25 June 2019 (diff | hist) . . (-1) . . MSI Protocol (→The key role of MC_Ack) (current)
- 13:54, 25 June 2019 (diff | hist) . . (-51) . . MSI Protocol (→Limited directory memory)
- 13:52, 25 June 2019 (diff | hist) . . (+306) . . L2 and Directory cache controller (→Message Generator)
- 13:47, 25 June 2019 (diff | hist) . . (+1) . . L2 and Directory cache controller (→Replacement Logic)
- 13:47, 25 June 2019 (diff | hist) . . (-141) . . L2 and Directory cache controller (→Replacement Logic)
- 13:13, 25 June 2019 (diff | hist) . . (-36) . . L2 and Directory cache controller (→Replacement Logic)
- 13:01, 25 June 2019 (diff | hist) . . (-254) . . L2 and Directory cache controller (→Cache Update Logic)
- 12:54, 25 June 2019 (diff | hist) . . (-236) . . L2 and Directory cache controller (→TSHR Update Logic)
- 12:49, 25 June 2019 (diff | hist) . . (+99) . . L2 and Directory cache controller (→Protocol ROM)
- 12:49, 25 June 2019 (diff | hist) . . (+10) . . L2 and Directory cache controller (→Protocol ROM)
- 12:47, 25 June 2019 (diff | hist) . . (+1,691) . . L2 and Directory cache controller (→Stage 3)
- 12:33, 25 June 2019 (diff | hist) . . (-4) . . L2 and Directory cache controller (→Stage 2)
- 12:28, 25 June 2019 (diff | hist) . . (+24) . . L2 and Directory cache controller (→Stage 1)
- 12:19, 25 June 2019 (diff | hist) . . (+2) . . L2 and Directory cache controller (→Stage 1)
- 12:04, 25 June 2019 (diff | hist) . . (+21) . . L2 and Directory cache controller
- 11:58, 25 June 2019 (diff | hist) . . (+13) . . L1 Cache Controller (→Cache Update Logic)
- 11:50, 25 June 2019 (diff | hist) . . (+36) . . L1 Cache Controller (→MSHR Update Logic)
- 11:43, 25 June 2019 (diff | hist) . . (+6) . . L1 Cache Controller (→Replacement Logic)
- 11:40, 25 June 2019 (diff | hist) . . (+3) . . L1 Cache Controller (→Issuing a Request)
- 11:39, 25 June 2019 (diff | hist) . . (-4) . . L1 Cache Controller (→Request Issue Signals)
- 11:39, 25 June 2019 (diff | hist) . . (+358) . . L1 Cache Controller (→Stage 1)
- 11:28, 25 June 2019 (diff | hist) . . (-4) . . L1 Cache Controller (→Assumptions)
- 18:32, 21 June 2019 (diff | hist) . . (-102) . . L1 Cache Controller (→MSHR Update Logic)
- 18:18, 21 June 2019 (diff | hist) . . (+174) . . L1 Cache Controller (→Replacement Logic)
- 18:06, 21 June 2019 (diff | hist) . . (-34) . . L1 Cache Controller (→Protocol ROM)
- 17:20, 21 June 2019 (diff | hist) . . (+83) . . L1 Cache Controller (→Protocol ROM)
- 17:17, 21 June 2019 (diff | hist) . . (+28) . . L1 Cache Controller (→MSHR)
- 17:14, 21 June 2019 (diff | hist) . . (-110) . . L1 Cache Controller (→Hit/miss logic)
- 17:07, 21 June 2019 (diff | hist) . . (+27) . . L1 Cache Controller (→Requests Scheduler)
- 17:05, 21 June 2019 (diff | hist) . . (+2) . . L1 Cache Controller (→Request Issue Signals)
- 17:05, 21 June 2019 (diff | hist) . . (+1) . . L1 Cache Controller (→Request Issue Signals)
- 16:54, 21 June 2019 (diff | hist) . . (+64) . . L1 Cache Controller (→Request Issue Signals)
- 16:48, 21 June 2019 (diff | hist) . . (+377) . . L1 Cache Controller (→Stall Protocol ROMs)
- 16:45, 21 June 2019 (diff | hist) . . (-25) . . L1 Cache Controller (→Stall Protocol ROMs)
- 16:38, 21 June 2019 (diff | hist) . . (+4) . . L1 Cache Controller (→MSHR Signals)
- 16:37, 21 June 2019 (diff | hist) . . (0) . . L1 Cache Controller (→Assumptions)
- 16:36, 21 June 2019 (diff | hist) . . (+3) . . L1 Cache Controller (→Assumptions)
- 16:36, 21 June 2019 (diff | hist) . . (+26) . . L1 Cache Controller
- 16:31, 21 June 2019 (diff | hist) . . (+15) . . MSI Protocol (→The key role of MC_Ack)
- 16:27, 21 June 2019 (diff | hist) . . (+80) . . MSI Protocol (→The key role of MC_Ack)
- 16:07, 21 June 2019 (diff | hist) . . (+24) . . MSI Protocol (→The key role of MC_Ack)
- 16:04, 21 June 2019 (diff | hist) . . (+344) . . MSI Protocol (→Transitions of state N)
- 15:55, 21 June 2019 (diff | hist) . . (-115) . . MSI Protocol (→Limited directory memory)
- 15:49, 21 June 2019 (diff | hist) . . (+27) . . Network interface (→General architecture)
- 15:47, 21 June 2019 (diff | hist) . . (+10) . . Network (→Data structures)
- 15:28, 21 June 2019 (diff | hist) . . (+34) . . MC Item (→Running threads) (current)
- 15:28, 21 June 2019 (diff | hist) . . (+9) . . MC Item (→Setting PCs)
- 15:27, 21 June 2019 (diff | hist) . . (+1) . . MC Item
- 15:25, 21 June 2019 (diff | hist) . . (+7) . . Heterogeneous Tile (→Adding custom logic)
- 15:24, 21 June 2019 (diff | hist) . . (+22) . . Heterogeneous Tile (→Synchronization Interface)
- 15:23, 21 June 2019 (diff | hist) . . (+11) . . Heterogeneous Tile
- 15:21, 21 June 2019 (diff | hist) . . (+18) . . MC System (→H2C tile)
(newest | oldest) View (newer 100 | older 100) (20 | 50 | 100 | 250 | 500)