User contributions
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- 21:32, 31 March 2019 (diff | hist) . . (-33) . . The NaplesPU Hardware architecture (→Hardware sections)
- 21:31, 31 March 2019 (diff | hist) . . (-5) . . The NaplesPU Hardware architecture (→Hardware sections)
- 21:30, 31 March 2019 (diff | hist) . . (+3,119) . . N SC Logger (Created page with "The nu+ single core system provides a logging system. The module nuplus_core_logger logs the last transactions to the main memory, logging all the memory request issued by the...")
- 21:09, 31 March 2019 (diff | hist) . . (+246) . . SC Synch
- 21:05, 31 March 2019 (diff | hist) . . (+17) . . SC Synch
- 21:04, 31 March 2019 (diff | hist) . . (+1,467) . . N SC Synch (Created page with "The single core version of the nu+ architecture shares the same synchronization master module, namely synchronization_core, of the many core version. The synchronization_core...")
- 20:56, 31 March 2019 (diff | hist) . . (-10) . . The NaplesPU Hardware architecture (→Hardware sections)
- 20:55, 31 March 2019 (diff | hist) . . (-3) . . SC System
- 20:55, 31 March 2019 (diff | hist) . . (+1,641) . . N SC System (Created page with "The nu+ single core system is defined in the ''nuplus_system.sv'' module, under src/sc/system folder. The single core version instantiates the following modules: # nu+ core:...")
- 16:08, 27 March 2019 (diff | hist) . . (+706) . . Basic comps (→Control Logic Support)
- 16:04, 27 March 2019 (diff | hist) . . (+742) . . Basic comps (→Control Logic Support)
- 15:57, 27 March 2019 (diff | hist) . . (-43) . . The NaplesPU Hardware architecture
- 15:56, 27 March 2019 (diff | hist) . . (+160) . . Basic comps
- 15:54, 27 March 2019 (diff | hist) . . (+21) . . Basic comps
- 15:51, 27 March 2019 (diff | hist) . . (+1,683) . . Basic comps
- 15:35, 27 March 2019 (diff | hist) . . (+1,606) . . Basic comps
- 14:29, 27 March 2019 (diff | hist) . . (+750) . . N Basic comps (Created page with "The following section describes all the basic components used in the design of the system. Such components are located in the src/common folder and due to their extensive use...")
- 14:13, 27 March 2019 (diff | hist) . . (-104) . . Network interface
- 14:05, 27 March 2019 (diff | hist) . . (-34) . . Network router
- 13:57, 27 March 2019 (diff | hist) . . (-6) . . Network (→Implementation)
- 13:56, 27 March 2019 (diff | hist) . . (+13) . . Network
- 13:46, 27 March 2019 (diff | hist) . . (+38) . . Synchronization
- 13:44, 27 March 2019 (diff | hist) . . (+1,156) . . Synchronization
- 13:13, 27 March 2019 (diff | hist) . . (+6) . . Synchronization
- 13:13, 27 March 2019 (diff | hist) . . (-8) . . Synchronization
- 13:12, 27 March 2019 (diff | hist) . . (0) . . N File:Sync core.png (current)
- 13:12, 27 March 2019 (diff | hist) . . (+1,195) . . Synchronization (→Synchronization Core)
- 16:53, 26 March 2019 (diff | hist) . . (+4) . . Network router
- 16:51, 26 March 2019 (diff | hist) . . (-5) . . The NaplesPU Hardware architecture (→Hardware sections)
- 16:51, 26 March 2019 (diff | hist) . . (+223) . . Include (→Coherence Defines)
- 16:50, 26 March 2019 (diff | hist) . . (+1,494) . . Include
- 16:44, 26 March 2019 (diff | hist) . . (+407) . . Include (→Synchronization Defines)
- 16:43, 26 March 2019 (diff | hist) . . (+514) . . Include
- 16:40, 26 March 2019 (diff | hist) . . (+6) . . Include (→Network Defines)
- 16:40, 26 March 2019 (diff | hist) . . (+28) . . Include (→Network Defines)
- 16:39, 26 March 2019 (diff | hist) . . (+938) . . Include
- 16:27, 26 March 2019 (diff | hist) . . (+625) . . Include
- 16:21, 26 March 2019 (diff | hist) . . (-19) . . The NaplesPU Hardware architecture
- 16:20, 26 March 2019 (diff | hist) . . (+229) . . Include
- 16:19, 26 March 2019 (diff | hist) . . (+679) . . Include
- 16:09, 26 March 2019 (diff | hist) . . (+17) . . Include
- 16:08, 26 March 2019 (diff | hist) . . (+1,741) . . Include
- 15:49, 26 March 2019 (diff | hist) . . (+1,722) . . N Include (Created page with "== Nu+ Defines == == User Defines == Furthermore, DISPLAY variables are defined, all commented by default. When a DISPLAY variable is active, it generates a file, under a...")
- 14:23, 26 March 2019 (diff | hist) . . (+106) . . Core (→Rollback handler)
- 14:21, 26 March 2019 (diff | hist) . . (+2,112) . . Core
- 19:53, 25 March 2019 (diff | hist) . . (+78) . . Core (→Decode stage)
- 19:50, 25 March 2019 (diff | hist) . . (+147) . . Core (→Output logic)
- 19:48, 25 March 2019 (diff | hist) . . (+1,312) . . Core
- 18:28, 25 March 2019 (diff | hist) . . (+6) . . Core
- 18:28, 25 March 2019 (diff | hist) . . (-22) . . Core
- 18:27, 25 March 2019 (diff | hist) . . (+572) . . Core
- 18:18, 25 March 2019 (diff | hist) . . (-9) . . Core
- 18:17, 25 March 2019 (diff | hist) . . (0) . . N File:Nup pipe.png (current)
- 18:15, 25 March 2019 (diff | hist) . . (-26) . . Core
- 18:14, 25 March 2019 (diff | hist) . . (+33) . . Core
- 18:13, 25 March 2019 (diff | hist) . . (+43) . . The NaplesPU Hardware architecture
- 18:11, 25 March 2019 (diff | hist) . . (+29) . . The NaplesPU Hardware architecture
- 18:07, 25 March 2019 (diff | hist) . . (+49) . . The NaplesPU Hardware architecture
- 18:03, 25 March 2019 (diff | hist) . . (-3) . . The NaplesPU Hardware architecture
- 18:01, 25 March 2019 (diff | hist) . . (+56) . . The NaplesPU Hardware architecture
- 17:59, 25 March 2019 (diff | hist) . . (+43) . . The NaplesPU Hardware architecture
- 17:59, 25 March 2019 (diff | hist) . . (+52) . . The NaplesPU Hardware architecture
- 17:56, 25 March 2019 (diff | hist) . . (+1) . . The NaplesPU Hardware architecture
- 17:56, 25 March 2019 (diff | hist) . . (+15) . . The NaplesPU Hardware architecture
- 17:55, 25 March 2019 (diff | hist) . . (-72) . . The NaplesPU Hardware architecture (→Single Core)
- 17:55, 25 March 2019 (diff | hist) . . (+82) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:54, 25 March 2019 (diff | hist) . . (-62) . . The NaplesPU Hardware architecture (→Common)
- 17:54, 25 March 2019 (diff | hist) . . (-5) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:53, 25 March 2019 (diff | hist) . . (+5) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:52, 25 March 2019 (diff | hist) . . (+2) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:52, 25 March 2019 (diff | hist) . . (+9) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:52, 25 March 2019 (diff | hist) . . (+67) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:51, 25 March 2019 (diff | hist) . . (-95) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:49, 25 March 2019 (diff | hist) . . (+83) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:58, 6 March 2019 (diff | hist) . . (+37) . . L1 Cache Controller (→Protocol ROM)
- 17:51, 4 March 2019 (diff | hist) . . (+6) . . The NaplesPU Hardware architecture (→Hardware sections)
- 17:49, 4 December 2018 (diff | hist) . . (-33) . . L1 Cache Controller (→Stage 4)
- 18:42, 28 May 2018 (diff | hist) . . (-1) . . Core (→Writeback stage)
- 18:12, 28 May 2018 (diff | hist) . . (+24) . . Core (→Branch unit)
- 18:08, 28 May 2018 (diff | hist) . . (+48) . . Core (→Control registers)
- 18:08, 28 May 2018 (diff | hist) . . (+1,068) . . Core (→Integer Arithmetic & Logic unit)
- 17:57, 28 May 2018 (diff | hist) . . (+287) . . Core (→Operand fetch stage)
- 17:37, 28 May 2018 (diff | hist) . . (+200) . . Core (→Instruction scheduler stage)
- 17:33, 28 May 2018 (diff | hist) . . (-1,077) . . Core (→Instruction scheduler stage)
- 17:30, 28 May 2018 (diff | hist) . . (+25) . . Core (→Instruction scheduler stage)
- 17:28, 28 May 2018 (diff | hist) . . (+2,010) . . Core (→Instruction scheduler stage)
- 17:26, 28 May 2018 (diff | hist) . . (+34) . . Core (→Decode stage)
- 16:52, 28 May 2018 (diff | hist) . . (+902) . . Core (→Decode stage)
- 16:42, 28 May 2018 (diff | hist) . . (-50) . . Core (→Decode stage)
- 16:40, 28 May 2018 (diff | hist) . . (-95) . . Core (→Decode stage)
- 16:39, 28 May 2018 (diff | hist) . . (+225) . . Core (→Instruction Fetch Stage)
- 15:53, 28 May 2018 (diff | hist) . . (+93) . . Core (→Instruction fetch stage)
- 14:15, 20 December 2017 (diff | hist) . . (+22) . . L1 Cache Controller (→Requests Scheduler)
- 14:00, 20 December 2017 (diff | hist) . . (+4) . . L2 and Directory cache controller (→Cache Update Logic)
- 13:57, 20 December 2017 (diff | hist) . . (+15) . . L2 and Directory cache controller (→TSHR Update Logic)
- 13:53, 20 December 2017 (diff | hist) . . (+14) . . L2 and Directory cache controller (→Protocol ROM)
- 20:22, 30 October 2017 (diff | hist) . . (+78) . . Core (→Control register)
- 19:52, 30 October 2017 (diff | hist) . . (+1,454) . . Core (→Instruction scheduler stage)
- 15:04, 25 September 2017 (diff | hist) . . (+106) . . Core (→Thread controller)
- 14:49, 25 September 2017 (diff | hist) . . (+137) . . Core (→Writeback stage)
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