Difference between revisions of "SC System"

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The nu+ single core system is defined in the ''nuplus_system.sv'' module, under src/sc/system folder. The following figure depicts the organization of the nu+ Single Core version:
 
The nu+ single core system is defined in the ''nuplus_system.sv'' module, under src/sc/system folder. The following figure depicts the organization of the nu+ Single Core version:
  
[[File:Nup sc system.png|900px|Single Core System]]
+
[[File:Nup sc system.png|470px|Single Core System]]
  
 
The single core version instantiates the following modules:
 
The single core version instantiates the following modules:

Revision as of 15:56, 30 May 2019

The nu+ single core system is defined in the nuplus_system.sv module, under src/sc/system folder. The following figure depicts the organization of the nu+ Single Core version:

Single Core System

The single core version instantiates the following modules:

  1. nu+ core: module nuplus_core (described in nu+ core architecture)
  2. item interface: nuplus_item_interface module, allows host-device communication and performance info fetching.
  3. transaction logger: nuplus_core_logger module, which logs both incoming responses from the main memory and issued requests from the core to the memory. This module stores up to CORE_LOG_SIZE (default 512) for the core issued transactions, and MEM_LOG_SIZE (default 512)
  4. core interface: core_interface module, connects the nu+ core and the cache-controller for the single core version, module sc_cache_controller
  5. cache controller: sc_cache_controller module, the cache controller for the single core version of the nu+ architecture, described in Cache Controller
  6. system bus: mux_multimaster module, shared multi-master bus. It allows both the core and the host-interface to concurrently access the main memory and custom devices
  7. test device: io_device_test module, an example of a memory mapped custom device in the nu+ system
  8. synchronization core: synchronization_core module, acts as the synchronization master allowing thread synchronization through barriers. The module is the same as the many core version, although it requires minor adjustments:
assign network_available     = 1'b1;
assign ni_account_mess_valid = c2n_account_valid;

Since the single core version of the system has no network, the network availability input port has to be constantly high.