Difference between revisions of "NaplesPURegisterInfo.td"
From NaplesPU Documentation
(Created page with "The NuPlusRegisterInfo.td is used to define the nu+ hw registers and the nu+ register classes. The registers definition is done creating two support classes '''NuPlusGPRReg'...") |
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The NuPlusRegisterInfo.td is used to define the nu+ hw registers and the nu+ register classes. | The NuPlusRegisterInfo.td is used to define the nu+ hw registers and the nu+ register classes. | ||
| − | The registers definition is done creating two support classes '''NuPlusGPRReg''' and '''NuPlus64GPRReg'''. The first one is used to define 32- | + | The registers definition is done creating two support classes '''NuPlusGPRReg''' and '''NuPlus64GPRReg'''. The first one is used to define 32-bit wide registers while the second is used to define 64-bit wide registers. We made this distinction because the hardware uses the same register for both 32 and 64 bits wide variables. Thus a 64-bit wide register is composed by a couple of 32-bit wide register, using the even sub-register to contain the 32 less significant bits, while the odd sub-register holds the 32 most significant bits. |
| + | |||
| + | <syntaxhighlight lang="c" line='line'> | ||
| + | // NuPlus 32-bit registers | ||
| + | class NuPlusGPRReg<bits<16> Enc, string n> : NuPlusReg<Enc, n>; | ||
| + | |||
| + | // NuPlus pairs of 32-bit registers | ||
| + | class NuPlus64GPRReg<bits<16> Enc, string n, list<Register> subregs> | ||
| + | : NuPlusRegWithSubRegs<Enc, n, subregs> { | ||
| + | let SubRegIndices = [sub_even, sub_odd]; | ||
| + | let CoveredBySubRegs = 1; | ||
| + | } | ||
| + | </syntaxhighlight> | ||
| + | |||
| + | Note that the '''NuPlus64GPRReg''' uses '''SubRegIndices''' to index a specific 32-bit wide sub-register. In particular, '''sub_even''' indexes the even sub-register, while '''sub_odd''' indexes the odd sub-register. | ||
| + | |||
| + | Two loops are used to define the architecture general purpose registers. | ||
| + | |||
| + | <syntaxhighlight lang="c" line='line'> | ||
| + | // General Purpose scalar registers | ||
| + | foreach i = 0-57 in { | ||
| + | def S#i : NuPlusGPRReg<i, "s"#i>, DwarfRegNum<[i]>; | ||
| + | } | ||
| + | |||
| + | //trap register | ||
| + | def TR_REG : NuPlusGPRReg<58, "tr">, DwarfRegNum<[58]>; | ||
| + | //mask register | ||
| + | def MR_REG : NuPlusGPRReg<59, "rm">, DwarfRegNum<[59]>; | ||
| + | //frame pointer | ||
| + | def FP_REG : NuPlusGPRReg<60, "fp">, DwarfRegNum<[60]>; | ||
| + | //stack pointer | ||
| + | def SP_REG : NuPlusGPRReg<61, "sp">, DwarfRegNum<[61]>; | ||
| + | //return address | ||
| + | def RA_REG : NuPlusGPRReg<62, "ra">, DwarfRegNum<[62]>; | ||
| + | //PC | ||
| + | def PC_REG : NuPlusGPRReg<63, "pc">, DwarfRegNum<[63]>; | ||
| + | |||
| + | // General Purpose vectorial registers | ||
| + | foreach i = 0-63 in { | ||
| + | def V#i : NuPlusGPRReg<i, "v"#i>, DwarfRegNum<[!add(i, 64)]>; | ||
| + | } | ||
| + | </syntaxhighlight> | ||
| + | |||
| + | Note also the definition of the special registers. | ||
Revision as of 16:42, 27 September 2017
The NuPlusRegisterInfo.td is used to define the nu+ hw registers and the nu+ register classes.
The registers definition is done creating two support classes NuPlusGPRReg and NuPlus64GPRReg. The first one is used to define 32-bit wide registers while the second is used to define 64-bit wide registers. We made this distinction because the hardware uses the same register for both 32 and 64 bits wide variables. Thus a 64-bit wide register is composed by a couple of 32-bit wide register, using the even sub-register to contain the 32 less significant bits, while the odd sub-register holds the 32 most significant bits.
// NuPlus 32-bit registers
class NuPlusGPRReg<bits<16> Enc, string n> : NuPlusReg<Enc, n>;
// NuPlus pairs of 32-bit registers
class NuPlus64GPRReg<bits<16> Enc, string n, list<Register> subregs>
: NuPlusRegWithSubRegs<Enc, n, subregs> {
let SubRegIndices = [sub_even, sub_odd];
let CoveredBySubRegs = 1;
}Note that the NuPlus64GPRReg uses SubRegIndices to index a specific 32-bit wide sub-register. In particular, sub_even indexes the even sub-register, while sub_odd indexes the odd sub-register.
Two loops are used to define the architecture general purpose registers.
// General Purpose scalar registers
foreach i = 0-57 in {
def S#i : NuPlusGPRReg<i, "s"#i>, DwarfRegNum<[i]>;
}
//trap register
def TR_REG : NuPlusGPRReg<58, "tr">, DwarfRegNum<[58]>;
//mask register
def MR_REG : NuPlusGPRReg<59, "rm">, DwarfRegNum<[59]>;
//frame pointer
def FP_REG : NuPlusGPRReg<60, "fp">, DwarfRegNum<[60]>;
//stack pointer
def SP_REG : NuPlusGPRReg<61, "sp">, DwarfRegNum<[61]>;
//return address
def RA_REG : NuPlusGPRReg<62, "ra">, DwarfRegNum<[62]>;
//PC
def PC_REG : NuPlusGPRReg<63, "pc">, DwarfRegNum<[63]>;
// General Purpose vectorial registers
foreach i = 0-63 in {
def V#i : NuPlusGPRReg<i, "v"#i>, DwarfRegNum<[!add(i, 64)]>;
}Note also the definition of the special registers.
