NaplesPU.td

//===-- NuPlus.td - Describe the NuPlus Target Machine -------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===// // Target-independent interfaces which we are implementing //===----------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===//

include "NuPlusRegisterInfo.td" include "NuPlusCallingConv.td" include "NuPlusInstrInfo.td"

def NuPlusInstrInfo : InstrInfo;

def NuPlusAsmParser : AsmParser {

 bit ShouldEmitMatchRegisterName = 1;

}

//===----------------------------------------------------------------------===// // Declare the target which we are implementing //===----------------------------------------------------------------------===//

def NuPlusAsmWriter : AsmWriter {

 string AsmWriterClassName  = "InstPrinter";
 bit isMCAsmWriter = 1;

}

def : Processor<"nuplus", NoItineraries, []>;

def NuPlus : Target {

 // Pull in Instruction Info:
 let InstructionSet = NuPlusInstrInfo;
 let AssemblyParsers  = [NuPlusAsmParser];
 let AssemblyWriters = [NuPlusAsmWriter];

} </syntaxhighlight>