Difference between revisions of "NaplesPU.td"

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(Undo revision 1369 by Francesco (talk))
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[[Category:Tablegen Files]]
 
[[Category:Tablegen Files]]
//===-- NuPlus.td - Describe the NuPlus Target Machine -------*- tablegen -*-===//
+
The NuPlus.td file contains the definition of the Target class '''NuPlus''' (defined in "compiler/include/llvm/Target/Target.td"). The file also contains the definition of the '''NuPlusInstrInfo''', '''NuPlusAsmParser''' and '''NuPlusAsmWriter''' required by the '''Target''' class. In addition, we avoid using instruction itineraries for scheduling. Itineraries are details reservation tables for each instruction class.  
//
 
//                    The LLVM Compiler Infrastructure
 
//
 
// This file is distributed under the University of Illinois Open Source
 
// License. See LICENSE.TXT for details.
 
//
 
//===----------------------------------------------------------------------===//
 
//
 
//
 
//===----------------------------------------------------------------------===//
 
  
//===----------------------------------------------------------------------===//
+
<syntaxhighlight lang="c" line='line'>
// Target-independent interfaces which we are implementing
 
//===----------------------------------------------------------------------===//
 
 
 
include "llvm/Target/Target.td"
 
 
 
//===----------------------------------------------------------------------===//
 
// Register File, Calling Conv, Instruction Descriptions
 
//===----------------------------------------------------------------------===//
 
  
 
include "NuPlusRegisterInfo.td"
 
include "NuPlusRegisterInfo.td"
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def NuPlusInstrInfo : InstrInfo;
 
def NuPlusInstrInfo : InstrInfo;
  
 +
//.s file parsing
 
def NuPlusAsmParser : AsmParser {
 
def NuPlusAsmParser : AsmParser {
 +
  // the target do not have multiple names for registers and, 
 +
  // hence, do not need a hand written register name matcher.
 
   bit ShouldEmitMatchRegisterName = 1;
 
   bit ShouldEmitMatchRegisterName = 1;
 
}
 
}
  
//===----------------------------------------------------------------------===//
+
//.s file writer
// Declare the target which we are implementing
 
//===----------------------------------------------------------------------===//
 
 
 
 
def NuPlusAsmWriter : AsmWriter {
 
def NuPlusAsmWriter : AsmWriter {
 
   string AsmWriterClassName  = "InstPrinter";
 
   string AsmWriterClassName  = "InstPrinter";
 +
  // this assembly writer if for an MC emitter (MCInst).
 
   bit isMCAsmWriter = 1;
 
   bit isMCAsmWriter = 1;
 
}
 
}

Revision as of 13:55, 5 April 2019

The NuPlus.td file contains the definition of the Target class NuPlus (defined in "compiler/include/llvm/Target/Target.td"). The file also contains the definition of the NuPlusInstrInfo, NuPlusAsmParser and NuPlusAsmWriter required by the Target class. In addition, we avoid using instruction itineraries for scheduling. Itineraries are details reservation tables for each instruction class.

include "NuPlusRegisterInfo.td"
include "NuPlusCallingConv.td"
include "NuPlusInstrInfo.td"

def NuPlusInstrInfo : InstrInfo;

//.s file parsing
def NuPlusAsmParser : AsmParser {
  // the target do not have multiple names for registers and,  
  // hence, do not need a hand written register name matcher.
  bit ShouldEmitMatchRegisterName = 1;
}

//.s file writer
def NuPlusAsmWriter : AsmWriter {
  string AsmWriterClassName  = "InstPrinter";
  // this assembly writer if for an MC emitter (MCInst).
  bit isMCAsmWriter = 1;
}

def : Processor<"nuplus", NoItineraries, []>;

def NuPlus : Target {
  // Pull in Instruction Info:
  let InstructionSet = NuPlusInstrInfo;
  let AssemblyParsers  = [NuPlusAsmParser];
  let AssemblyWriters = [NuPlusAsmWriter];
}