Difference between revisions of "NaplesPU.td"
From NaplesPU Documentation
m (Francesco moved page NuPlus.td to NaplesPU.td) |
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| Line 1: | Line 1: | ||
[[Category:Tablegen Files]] | [[Category:Tablegen Files]] | ||
| − | The | + | The NaplesPU.td file contains the definition of the Target class '''NaplesPU''' (defined in "compiler/include/llvm/Target/Target.td"). The file also contains the definition of the '''NaplesPUInstrInfo''', '''NaplesPUAsmParser''' and '''NaplesPUAsmWriter''' required by the '''Target''' class. In addition, we avoid using instruction itineraries for scheduling. Itineraries are details reservation tables for each instruction class. |
<syntaxhighlight lang="c" line='line'> | <syntaxhighlight lang="c" line='line'> | ||
| − | //===-- | + | //===-- NaplesPU.td - Describe the NaplesPU Target Machine -------*- tablegen -*-===// |
// | // | ||
// The LLVM Compiler Infrastructure | // The LLVM Compiler Infrastructure | ||
| Line 9: | Line 9: | ||
// This file is distributed under the University of Illinois Open Source | // This file is distributed under the University of Illinois Open Source | ||
// License. See LICENSE.TXT for details. | // License. See LICENSE.TXT for details. | ||
| − | // | + | //MCCodeEmitter/===----------------------------------------------------------------------===// |
| − | |||
// | // | ||
// | // | ||
| Line 25: | Line 24: | ||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||
| − | include " | + | include "NaplesPURegisterInfo.td" |
| − | include " | + | include "NaplesPUCallingConv.td" |
| − | include " | + | include "NaplesPUInstrInfo.td" |
| − | def | + | def NaplesPUInstrInfo : InstrInfo; |
| − | def | + | def NaplesPUAsmParser : AsmParser { |
bit ShouldEmitMatchRegisterName = 1; | bit ShouldEmitMatchRegisterName = 1; | ||
} | } | ||
| Line 39: | Line 38: | ||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||
| − | def | + | def NaplesPUAsmWriter : AsmWriter { |
string AsmWriterClassName = "InstPrinter"; | string AsmWriterClassName = "InstPrinter"; | ||
bit isMCAsmWriter = 1; | bit isMCAsmWriter = 1; | ||
} | } | ||
| − | def : Processor<" | + | def : Processor<"naplespu", NoItineraries, []>; |
| − | def | + | def NaplesPU : Target { |
// Pull in Instruction Info: | // Pull in Instruction Info: | ||
| − | let InstructionSet = | + | let InstructionSet = NaplesPUInstrInfo; |
| − | let AssemblyParsers = [ | + | let AssemblyParsers = [NaplesPUAsmParser]; |
| − | let AssemblyWriters = [ | + | let AssemblyWriters = [NaplesPUAsmWriter]; |
} | } | ||
</syntaxhighlight> | </syntaxhighlight> | ||
Latest revision as of 16:55, 21 June 2019
The NaplesPU.td file contains the definition of the Target class NaplesPU (defined in "compiler/include/llvm/Target/Target.td"). The file also contains the definition of the NaplesPUInstrInfo, NaplesPUAsmParser and NaplesPUAsmWriter required by the Target class. In addition, we avoid using instruction itineraries for scheduling. Itineraries are details reservation tables for each instruction class.
//===-- NaplesPU.td - Describe the NaplesPU Target Machine -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//MCCodeEmitter/===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//
include "NaplesPURegisterInfo.td"
include "NaplesPUCallingConv.td"
include "NaplesPUInstrInfo.td"
def NaplesPUInstrInfo : InstrInfo;
def NaplesPUAsmParser : AsmParser {
bit ShouldEmitMatchRegisterName = 1;
}
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
def NaplesPUAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
bit isMCAsmWriter = 1;
}
def : Processor<"naplespu", NoItineraries, []>;
def NaplesPU : Target {
// Pull in Instruction Info:
let InstructionSet = NaplesPUInstrInfo;
let AssemblyParsers = [NaplesPUAsmParser];
let AssemblyWriters = [NaplesPUAsmWriter];
}